Demo Data from EDBT 2026 / reviewers in the wild / expert
Hermann Mader
dblp:97/2815
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Integrated circuit design · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › technology computer-aided design
process modeling and simulation |
0.0 | 1 | 1988 | Simulation of dry etch processes by COMPOSITE · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Integrated circuit design
semiconductor process modeling |
0.0 | 1 | 1988 | Simulation of dry etch processes by COMPOSITE · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Methods — techniques the papers use, named apart from their topics
rate modeling · 0.0fitting functions · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Simulation of dry etch processes by COMPOSITEabstractAnetch simulator that allows modeling of dry etch processes by means of rates, fitting functions, and models is presented. Isotropic etching by chemically active neutrals, sputtering by energetic ions, and anisotropic etching by ion-induced chemistry can be considered. The simulation of secondary effects such as redeposition and trenching as well as polymerization effects is possible. Some applications are presented to demonstrate the possibilities of the new program. This etch simulator is part of the process modeling program COMPOSITE, which is able to simulate the complete fabrication process of integrated circuits.> Joachim Pelka, K. P. Muller, Hermann Mader |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |