A framework for the compaction of hierarchically specified layout sketches is proposed. The main advantage of the method is that it maintains the layout hierarchy. Thus, the produced output has the same efficient representation as the input and further efficient processing of the layout becomes possible.>

The authors present a new idea for designing a chip which computes the exact sum of arbitrarily many floating-point numbers, i.e. it can accumulate the floating-point numbers without cancellation. Such a chip is needed to provide a fast implementation of Kulisch arithmetic. This is a new theory of floating-point arithmetic which makes it possible to compute least significant bit accurate solutions to even ill-conditioned numerical problems. The proposed approach avoids the disadvantages of previously suggested designs which are too large, too slow, or consume too much power. The crucial point is a technique for a fast carry resolution in a long accumulator. It can also be implemented in software.>

A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area. An effective compaction system frees the designer from the details of the design rules, and hence, increases his or her productivity and on the other hand produces high quality layouts. A general framework for compaction on a torus is introduced. This problem comes up whenever an array of identical cells has to compacted. The framework is instantiated by several specific compaction algorithms: one-dimensional compaction without and with automatic job insertion and two-dimensional compaction.>

We give an Ο(n3·log n) time and Ο(n3) space algorithm for the continuous homotopic one layer routing problem. The main contribution is an extension of the sweep paradigm to a universal cover space of the plane.