John F. Beetem

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8ranked-venue papers
7as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 5 first-authorSystems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 71% Reconfigurable computing and FPGAs · 21% Parallel and multicore computing · 5%
Software engineering, system software, and programming languages
1 paper
Programming languages and type systems · 56% Compilers and program optimization · 44%

Topics — the 11 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.021998
Rebel: a clustering algorithm for look-up table FPGA's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Hierarchical topological sorting of apparent loops via partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Reconfigurable computing and FPGAs
FPGA architecture
0.011998
Rebel: a clustering algorithm for look-up table FPGA's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › physical design › placement
gate clustering
0.011998
Rebel: a clustering algorithm for look-up table FPGA's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation
hardware verification and test
0.011992
Hierarchical topological sorting of apparent loops via partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test
logic simulation
0.011992
Hierarchical topological sorting of apparent loops via partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Compilers and program optimization › parsing
incremental parsing
0.011991
Incremental Scanning and Parsing With Galaxy · IEEE Trans. Software Eng. 1991
Programming languages and type systems
language implementation
0.011991
Incremental Scanning and Parsing With Galaxy · IEEE Trans. Software Eng. 1991
Parallel and multicore computing › parallel architecture
parallel processor design
0.011985
The GF11 Supercomputer · ISCA 1985
High-performance computing
supercomputer architecture
0.011985
The GF11 Supercomputer · ISCA 1985
Programming languages and type systems
programming environment
0.011991
Incremental Scanning and Parsing With Galaxy · IEEE Trans. Software Eng. 1991
Parallel and multicore computing
multiprocessor system
0.011985
The GF11 Supercomputer · ISCA 1985

Methods — techniques the papers use, named apart from their topics

heuristic clustering · 0.0functional dependency propagation · 0.0rank ordering · 0.0partitioning · 0.0incremental scanning · 0.0incremental parsing · 0.0
YearPublicationVenuePosition
1998 Rebel: a clustering algorithm for look-up table FPGA's
abstract
Rebel is a new algorithm for clustering gates into k-input function blocks for look-up table field-programmable gate arrays (FPGA's). The algorithm propagates functional dependencies forward through a logic network, combining gates into clusters according to a heuristic metric. Rebel does a good job of handling reconvergent circuits, duplicating logic when it makes sense to do so, in addition, Rebel is fast, computing good clusters in near-linear time.
John F. Beetem
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1992 Visualizing optimization algorithms via rapid prototyping of graphical user interfaces
abstract
Graphical visualization of algorithm behavior can be a powerful technique for assessing the effectiveness of different algorithms and heuristics, provided that the graphical user interface (GUI) can be prototyped and modified quickly. Visualization was used to prototype a placement and routing package for the MITRE digital transform machine (DTM), a reconfigurable logic array. Use of the galaxy, programming language and environment greatly simplified GUI construction, allowing the prototyper to concentrate on placement and routing algorithms instead of the details of conventional GUI programming.>
John F. Beetem
RSP1
1992 Orthophrase extensibility in Galaxy
John F. Beetem, Anne F. Beetem, J. M. Park
Inf. Softw. Technol.1
1992 Hierarchical topological sorting of apparent loops via partitioning
abstract
Topological sorting (rank ordering) is a highly useful technique for ordering a set of objects according to a precedence relation, producing an ordered list suitable for processing. Applications for topological sorting include compiled logic simulation and timing analysis. While topological sorting is easily accomplished for flat combinational logic networks, hierarchical logic can be difficult to order because feedback may appear in the hierarchical representation even though it is not present in an equivalent flattened representation. This paper presents a new general solution to this problem and describes an efficient algorithm for topological sorting even in the presence of such apparent loops. Its application to hierarchical functional simulation of combinational and synchronous sequential logic is also discussed.>
John F. Beetem
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1991 Rapid implementation of hierarchical integrated simulators using Galaxy
abstract
The Galaxy CAD environment provides unique capabilities for rapid implementation and incorporation of tools into an integrated CAD framework. The author discusses in detail how novel hierarchical simulators can be added. Simulators are separated into generic and specific components. Galaxy provides generic functions so that programmers need only implement application-specific details such as data representation. This greatly reduces the quantity of code and expertise required by programmers to add new tools. Galaxy simulators and I/O tools, such as waveform editors, utilize a common communication protocol so that any I/O tool can be used as the front end of any simulator. Arbitrary combinations of tools can cooperate in the interactive multiple window environment.>
John F. Beetem
RSP1
1991 Incremental Scanning and Parsing With Galaxy
abstract
The algorithms and techniques used in incremental scanning and parsing of the Galaxy language are presented. Incremental compilers, programming environments that feature instantaneous change processing as well as the execution time efficiency of compiled programs and code development using the Galaxy language are discussed. It is shown that the algorithms guarantee minimal rescanning and reparsing are space and time efficient and are easily adapted to any language of equivalent class, including such languages as C and Pascal.>
John F. Beetem, Anne F. Beetem
IEEE Trans. Software Eng.1
1985 The GF11 Supercomputer
abstract
article Free Access Share on The GF11 supercomputer Authors: John Beetem IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Monty Denneau IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Don Weingarten IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 108–115https://doi.org/10.1145/327070.327139Published:01 June 1985Publication History 94citation465DownloadsMetricsTotal Citations94Total Downloads465Last 12 Months53Last 6 weeks14 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
John F. Beetem, Monty Denneau, Don Weingarten
ISCA1
1984 Test Generation for FET Switching Circuits
J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem
ITC3