Compute in-memory (CIM) is an exciting technique that minimizes data transport, maximizes memory throughput, and performs computation on the bitline of memory sub-arrays. This is especially interesting for machine learning applications, where increased memory bandwidth and analog domain computation offer improved area and energy efficiency. Unfortunately, CIM faces new challenges traditional CMOS architectures have avoided. In this work, we explore the impact of device variation (calibrated with measured data on foundry RRAM arrays) and propose a new class of error correcting codes (ECC) for hard and soft errors in CIM. We demonstrate single, double, and triple error correction offering over 16,000× reduction in bit error rate over a design without ECC and over 427× over prior work, while consuming only 29.1% area and 26.3% power overhead.

Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as$0.3\times $VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates.

The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, while satisfying a wide range of energy budgets, as well as platform cooling and power delivery constraints. Low-latency, burst-mode responsiveness, and scalable high-throughput performance must be delivered on demand for a range of thread-parallel, task-parallel, and data-parallel workloads covering traditional and emerging applications. This article discusses the challenges and opportunities for many-core SoC design in scaled CMOS process operating over a wide voltage-frequency range including near-threshold-voltage (NTV) that can meet the compute demands of the future at scale, flexibly, and efficiently. This article covers: 1) circuit design techniques for NTV cores; 2) mitigation techniques for within-die parameter variations via multivoltage frequency schemes; 3) digital integrated voltage regulators (VRs) for fine-grain and wide-range voltage modulation; and 4) radiation-induced soft error rate (SER) characterization and mitigation techniques to enable reliable operation at NTV. Silicon prototype examples will be used to illustrate the different techniques and highlight future research directions.

The high-performance and energy-efficient encryption engines have emerged as a key component for modern System-On-Chip (SoC) in various platforms including servers, desktops, mobile, and IoT edge devices. A key bottleneck to secure operation of encryption engines is leakage of information through various side-channels. For example, an adversary can extract the secret key by performing statistical analysis on measured power and electromagnetic (EM) emission signatures generated by the hardware during encryption. Countermeasures to such side-channel attacks often come at high power, area, or performance overheads. Therefore, design of side-channel secure encryption engines is a critical challenge for high-performance and/or power-/energy efficient operations. This paper reviews that although low-power requirement imposes critical challenge for side-channel security, but circuit techniques traditionally developed for power management also present new opportunities for side-channel resistance. As a case study, we review the feasibility of using integrated voltage regulator and dynamic voltage frequency scaling normally used for efficient power management, for increasing power-side-channel resistance of AES engines. The hardware measurement results from test-chip fabricated in 130nm process are presented to demonstrate the impact of power management circuits on side-channel security.

Many-core SoC designs in scaled CMOS process demand wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, as well as fine-grain multi-voltage design and spatio-temporal power management to deliver maximum performance under stringent thermal and energy constraints. Interconnect scaling bottlenecks, process-voltage-temperature variations and aging-induced degradation pose major challenges going forward. We present key circuit and design techniques for logic, memory and on-die interconnect networks that enable efficient, variation-tolerant and resilient many-core SoC designs in nanoscale CMOS.

Power attack is a critical challenge to security of encryption engines. Countermeasures to side-channel attacks often come at high power, area, or performance overhead. Therefore, design of side-channel secure encryption engines is a critical challenge for power-/resource-constrained platforms. This paper discusses that although low-power need imposes critical challenge for side-channel security, but circuit techniques traditionally developed for power management also present new opportunities for side-channel resistance. As a case-study, we show the feasibility of using integrated voltage regulator, normally used for efficient power management, for increasing side-channel resistance of AES engines.

The design of low power and side-channel-attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.

This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR to improve robustness of an encryption-engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.

Circuit and design techniques for fine-grain power management in manycore System-on-Chip (SoC) are presented. Recent advances in dynamic platform control techniques to enable (1) independent voltage-frequency domains, (2) dynamic power budget allocation to various blocks depending on workload, (3) fast dynamic voltage-frequency scaling and (4) fast activation and shutdown, are described. Future challenges and opportunities for complex manycore SoC designs with wide dynamic power-performance range, including near-threshold-voltage (NTV) operation, are summarized. Future trends in multi-voltage designs with integrated voltage regulators are highlighted.

Traditional synchronous VLSI design requires that all computations in a logic stage complete in one clock cycle. This leads to increasingly pessimistic design as technology scaling introduces increasingly significant parametric variations that result in an increasing performance variability. Alternatively, by allowing computations in a logic stage to complete in a variable number of clock cycles, variable-latency design provides relaxed timing constraints for average performance, area, and power consumption optimization. In this article, we present improved variable-latency design techniques including: (1) a generic minimum-intrusion variable-latency VLSI design paradigm, (2) a signal probability-based approximate prediction logic construction method for minimum misprediction rate at minimum cost, and (3) an application-specific cross-layer analysis methodology. Our experiments show that the proposed variable-latency design methodology on average reduces the computation latency by 26.80%(14.65%) at cost of 0.08%(3.4%) area and 0.4%(2.2%) energy consumption increase for the interger (floating point) unit of an open-source SPARC V8 processor LEON2 synthesized with a clock-cycle time between 1.97ns(3.49ns) and 5.96ns(13.74ns) based on the 45nm Nangate open cell library, while an automotive application-specific design further achieves an average latency reduction of 41.8%.

Resilient techniques are commonly employed for dynamic and static variation tolerance. In this paper, we present an adaptive clocking technique that achieves 31% throughput increase with 15% energy reduction, and an adaptive interconnect fabric technique that increases bandwidth by 63% with 14.6% energy reduction. We also discuss variations in many-core microprocessors and some techniques to enable a resilient many-core system on a chip.

Summary form only given. New technologies have led to an “explosion” of data available to document states and processes in very many fields. Tools of data mining are being used to extract relevant information. If this information is used in decision making, analytical statistics can provide formal tests comparing the outcomes of different scenarios. Statistics has traditionally dealt with limited information, both in terms of observations and numbers of variables explaining the states of these observations. Virtually all statistical hypothesis testing was developed for such scenarios, trying to make sense from limited data, often expensive to produce. Clinical trials and the steps in development of drugs before those clinical trials are a typical examples from human medicine.

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

Traditional processors are designed to guarantee error-free operation under worst-case (1) device & interconnect parameter variations resulting from less than ideal manufacturing process control; (2) static & erratic defects; (3) operating environments such as temperature excursions and voltage droops; (4) critical path activation and path delay degradations due to multiple inputs switching simultaneously in gates containing transistor stacks, or signal coupling from neighboring lines in interconnect paths; (5) speed degradation over the operating lifetime due to transistor aging under voltage, temperature & current stress; (6) early-life failures due to latent defect accelerations; and (7) soft error due to cosmic rays and alpha particle impacts. The voltage-frequency settings for all processors are set based on these infrequently encountered worst-case considerations, even though under typical conditions voltage can be pushed down further or frequency increased without causing errors for most of the processors, thus limiting both energy efficiency and performance in scaled CMOS technologies.

Conventional microprocessors require a clock frequency (F CLK ) guardband to ensure correct functionality during infrequent dynamic operating variations in supply voltage (V CC ), temperature, and transistor aging. Consequently, these inflexible designs cannot exploit opportunities for higher performance by increasing F CLK or lower energy by reducing V CC during favorable operating conditions. This presentation describes a 45nm resilient microprocessor with error-detection and recovery circuits to detect and correct timing errors from dynamic variations to mitigate the F CLK guardband, thus enabling higher performance or lower energy as compared to a conventional design. The microprocessor core supports two distinct error-detection designs and two separate error-recovery techniques, allowing a direct comparison of the relative trade-offs. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% V CC droop. In addition, the resilient circuits guide an adaptive clock controller that tracks recovery cycles and adapts to persistent variations by changing F CLK . The combination of error-detection and recovery circuits with dynamic adaptation allows the microprocessor to adapt to the operating environment to deliver maximum efficiency. The presentation concludes by discussing the opportunity of applying resilient techniques to enhance the dynamic operating range (i.e., high-performance and low-power modes) for microprocessors.

Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection sequential circuits with error recovery. These circuits mitigate the clock frequency guardbands for dynamic variations, thus improving microprocessor performance and energy-efficiency. These circuits are described with a focus on the different trade-offs in guardband reduction and design overhead. Opportunities for CAD to further enhance microprocessor performance and energy efficiency are offered.

For the first time, a new source of random threshold voltage (Vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, christened Work-Function Variation (WFV), is caused by the dependency of metal work-function on the orientation of its grains. A statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. This paper offers three major contributions for process, device and circuit designers. First, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of Vth fluctuation due to WFV. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN result in lower Vth fluctuation. Second, device engineers can benefit from the result of this work by evaluating the WFV level of various types of classical or non-classical metal-gate CMOS transistors. As an example, it is shown that FinFET transistors are less affected by WFV compared to FD-SOI and Bulk-Si devices due to their larger gate area. Third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. For instance, an SRAM cell is analyzed in the presence of Vthfluctuations due to WFV and it is shown that such variations can result in considerable performance and reliability degradation.

In this paper, an accurate approach for estimating SRAM dynamic stability is proposed. The conventional methods of SRAM stability estimation suffer from two major drawbacks: 1) using static failure criteria, such as static noise margin (SNM), which does not capture the transient and dynamic behavior of SRAM operation and 2) using quasi-Monte Carlo simulation, which approximates the failure distribution, resulting in large errors at the tails where the desired failure probabilities exist. These drawbacks are eliminated by employing a new distribution-independent, most-probable-failure-point search technique for accurate probability calculation along with accurate simulation-based dynamic failure criteria. Compared to previously published techniques, the proposed technique offers orders of magnitude improvement in accuracy. Furthermore, the proposed technique enables the correct evaluation of stability in real operation conditions and for different dynamic circuit techniques, such as dynamic write-back, where the conventional methods are not applicable.

We explore the power benefits of changing a microprocessor path histogram through circuit sizing based on statistical timing analysis and optimization (STAO) versus a deterministic timing approach that uses statistical design to establish a global guardband followed by conventional optimization (SDGG). Using an analytical modeling approach, we quantify the differences in total power between the two approaches while maintaining an equivalent performance distribution. For a relative 1σ random WID stage delay variation of 5% and representative microprocessor critical paths, the analysis indicates that the STAO approach enables ~2% power reduction over the SDGG approach. To achieve a 4% and 6% power reduction through the STAO approach, the process variation needs to increase by a factor of 2x and 4x, respectively.

We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower nonoptimal supply voltage which can underestimate the energy/operation by 8.2. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures. To further limit the effect of variations, and allow for a reduced power consumption, we analyzed the effects of clustering. It was shown that providing different voltages to each cluster can provide a further 10% reduction in energy/operation to a low-voltage parallel system, and that the savings by clustering increase as technology scales.

On-chip serial link buses have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics. However, it was noticed that serializing m-bits on a single interconnect (serial-link) increases the overall data switching activity. This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors. Two transition encoding schemes, to reduce the activity factor of serial links, are discussed and analyzed. The impact of the encoding schemes on the MCF between neighboring interconnects is also discussed. The analysis shows that both of the schemes provide significant reduction in the average activity factor and energy dissipation reduction, but each in a different range of input activity factors. The two encoding bus schemes were modeled in a 70nm CMOS technology, and compared to an unencoded serial link bus and a parallel line bus. Simulation results show that the transition encoded bus schemes reduce the overall energy dissipation of the unencoded serial link bus by up to 96%

SRAM arrays using differential sensing (DS) and single-ended sensing (SE) are designed and fabricated in a test chip and their power and performance behaviors are studied in this paper. Sense amplifier offset (DC condition), which is one of the main criterion to determine the required bit-line differential, is measured. A novel SE scheme is proposed to overcome the delay degradation due to large bit line leakage in scaled technology. With marginal switching power savings, the SE array is 56% slower than the DS array in 90 nm technology with a single high-Vt at 350 mV. The difference narrows down to 30% in low-Vt case. Using asymmetric cells, instead of symmetric cells, in single-ended large signal arrays improves delay by 3%, while the power consumption remains approximately the same.

Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnect with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%.

Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between them. Active shielding is another shielding technique in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This paper formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/=C/sub c//C/sub g/). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A suboptimal active shielding architecture with simpler hardware is also proposed. Theoretically, using the suboptimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit. However, due to the simpler shield encoding circuitry, simulation results show that the suboptimal active shielding architecture leads to higher overall energy savings compared to the optimal active shielding architectures.

We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower non-optimal supply voltage which can underestimate the energy/ operation by 8.2X. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures.

Die-to-die and within-die variations impact the frequency and power of fabricated dies, affecting functionality, performance, and revenue. Variation-tolerant circuits and post-silicon tuning techniques are important for minimizing the impacts of these variations. This paper describes several circuit techniques that can be employed to ensure efficient circuit operation in the presence of ever-increasing variations.

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus CB architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus SLB, transforms an n-bit conventional parallel-line bus into an n/m-line (serial-link) bus. The advantage of serial-link buses is that they have fewer lines, and if the bus width is kept the same, serial- link buses will have larger line width and spacing. Increasing the line width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the bus energy dissipation and maximizes the bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line buses, the serial-link bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.

This paper explores the effectiveness of the simultaneous application of pipelining and parallel processing as a total power (static plus dynamic) reduction technique in digital systems. Previous studies have been limited to either pipelining or parallel processing, but both techniques can be used together to reduce supply voltage at a fixed throughput point. According to our first-order analyses, there exist optimal combinations of pipelining depth and parallel processing width to minimize total power consumption. We show that the leakage power from both subthreshold and gate-oxide tunneling plays a significant role in determining the optimal combination of pipelining depth and parallel processing width. Our experiments are conducted with timing information derived from a 65nm technology and fanout-of-four (FO4) inverter chains. The experiments show that the optimal combinations of both pipelining and parallel processing - 8 /spl sim/ 12 /spl times/ FO4 logic depth pipelining with 2 /spl sim/ 3-wide parallel processing - can reduce the total power by as much as 40% compared to an optimal system using only pipelining or parallel processing alone. We extend our study to show how process parameter variations - an increasingly important factor in nanometer technologies - affects these results. Our analyses reveal that the variations shift the optimal points to shallower pipelining and narrower parallel processing - 12 /spl times/ FO4 logic depth with 2-wide parallel processing - at a fixed yield point.

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.

Fluctuations in intrinsic linear Vt, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σVT, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.

CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by sub-wavelength lithography, will pose a major challenge for design and reliability of future high performance microprocessors in nanometer technologies. In this paper, we present the impact of these variations on processor functionality, predictability and reliability. We propose design and CAD solutions for variation tolerance. We conclude this paper with soft error rate scaling trends and soft error tolerant circuits for reliability enhancement.

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.

Measurements on a prototype chip, implemented in a 150nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that 2X reduction in current variation is achievable across extremes of both process and temperature.

Technology scaling challenges the effectiveness of current-based test techniques such as I/sub DDQ/. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I/sub DDQ/ versus F/sub MAX/ (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I/sub DDQ/ versus temperature test can be deployed. Our data show that temperature (cooling from 110/spl deg/C to room) improved sensitivity of I/sub DDQ/ versus F/sub MAX/ two-parameter test by more than an order of magnitude (13.8/spl times/). The sensitivity can also be tuned by proper selection of a temperature range to match a required defect per million (DPM) level.

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.

We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.

This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10 nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose microprocessors are elucidated.

Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practice will have to change from deterministic design to probabilistic and statistical design. This paper discusses circuit techniques and design automation opportunities to overcome the challenges.

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict sub-threshold leakage power of such systems. In this paper, we present a sub-threshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18 mm CMOS confirms that the mean error of the model to be 4%. Comparisons of this model to two other existing models that do not take within-die threshold voltage variation into account are also presented.

In sub-100nm technology generation, transistor subthreshold leakage is 100-1000nA/μm for high performance microprocessor logic technology. As gate oxide thickness approaches sub-10Å regime, gate oxide leakage escalates to 10-100A/cm2. Junction leakages also become significant as doping levels around the junction approach 5X1018 cm-3. These excessive leakage currents contribute to large leakage power dissipation during (1) active operation, (2) standby or idle mode and (3) burn-in. In addition, excessive subthreshold leakage degrades noise margin or robustness of performance-critical circuits such as wide-OR domino gates, register files and cache. Large gate oxide leakage also limits circuit fanout. Therefore, high performance and low power processor designs must employ leakage power control techniques to alleviate active power dissipation and delivery challenges, extend battery life and prevent thermal runaway during burn-in. In addition, leakage-tolerant high performance circuits must be used to provide adequate circuit robustness.

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 /spl mu/m single-V/sub t/ and 0.13 /spl mu/m dual-V/sub t/ logic process technologies. Investigates its dependencies on channel length, target V/sub t/, temperature and technology generation. Shows that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V/sub t/ at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V/sub t/ values are low. A model is given that relates different transistor leakage components to full-chip leakage current, and is validated through test-chip measurements across a range of RBB values.

Article Share on Scaling of stack effect and its application for leakage reduction Authors: Siva Narendra Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA and Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Vivek De Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile , Dimitri Antoniadis Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Anantha Chandrakasan Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MAView Profile , Shekhar Borkar Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR Microprocessor Research Laboratories, Intel Corporation, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 195–200https://doi.org/10.1145/383082.383132Online:06 August 2001Publication History 140citation1,436DownloadsMetricsTotal Citations140Total Downloads1,436Last 12 Months24Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors Share on Authors: James Tschanz Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Siva Narendra Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Zhanping Chen Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Shekhar Borkar Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Manoj Sachdev Department of ECE, University of Waterloo, Canada Department of ECE, University of Waterloo, CanadaView Profile , Vivek De Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 147–152https://doi.org/10.1145/383082.383121Online:06 August 2001Publication History 39citation804DownloadsMetricsTotal Citations39Total Downloads804Last 12 Months50Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.

We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

Technology scaling challenges the effectiveness of current-based test techniques such as I/sub DDQ/. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I/sub DDQ/ versus F/sub MAX/ (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I/sub DDQ/ versus temperature test can be deployed. Our data show that temperature (cooling from 110/spl deg/C to room) improved sensitivity of I/sub DDQ/ Versus F/sub MAX/ two-parameter test by more than an order of magnitude (13.8X). The sensitivity can also be tuned by proper selection of a temperature range to match a required DPM level.

Dual threshold technique has been proposed to reduce leakage power in low v oltage and low p o w er circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance.Mixed-Vth (MVT) static CMOS design technique allows dierent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique.In this paper, a methodology for MVT CMOS circuit design is presented.Dierent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints.Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

Article Technology and design challenges for low power and high performance Share on Authors: Vivek De Intel Corporation, MicroComputer Research Labs, Hillsboro, OR Intel Corporation, MicroComputer Research Labs, Hillsboro, ORView Profile , Shekhar Borkar Intel Corporation, MicroComputer Research Labs, Hillsboro, OR Intel Corporation, MicroComputer Research Labs, Hillsboro, ORView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 163–168https://doi.org/10.1145/313817.313908Online:17 August 1999Publication History 220citation2,087DownloadsMetricsTotal Citations220Total Downloads2,087Last 12 Months64Last 6 weeks10 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology.We also show: (1) the optimum reverse body bias value reduces by -2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by -4X per generation under constant field technology scaling scenario.Optimum point occurs as a result of reduction in subthreshold leakage and an increase in junction band-to-band tunneling leakage with applied reverse bias.Therefore, new junction engineering techniques to reduce the bulk band-toband tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.

We demonstrate a new approach minimizing the total ofthe static and the dynamic power dissipation components in aCMOS logic network required to operate at a specified clockfrequency using joint optimization of both device and circuitdesigns for a specific logic schematic and activity profile.We present a new approach to designing ultra low-powerCMOS logic circuits by joint optimization of supply voltage,threshold voltage and device widths for a specified speedconstraints.The static (leakage) and dynamic (switching)energy components are considered and an efficient heuristicis developed that delivers over an order of magnitude savingsin power over conventional optimization methods.

Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60/spl deg/K above room temperature.

A novel quasi-adiabatic, precharge-evaluate logic family, Dynamic Adiabatic MOS (DAMOS), is proposed. Wave-pipelined DAMOS inverter chain datapaths in a 0.25 /spl mu/m, 2.5 V CMOS device technology are shown to successfully recycle 73% and 89% of the energy available from the power-clock in high-performance (200 MHz) and fixed-throughput (10 MHz) applications, respectively. DAMOS offers significantly smaller energy dissipation and device count per gate compared to previously reported dynamic quasi-adiabatic (but irreversible) logic families. Computational energy and power of a wave-pipelined DAMOS inverter chain (excluding dissipations in the power-clock generator) are 83% to 93% smaller than that consumed by its conventional Domino CMOS counterpart (excluding dissipations in the clock drivers) at identical operational throughputs. In addition, DAMOS provides one to three orders of magnitude reduction in peak power compared to Domino logic, indicating significant relaxation of electrical stress in both devices and interconnections. Novel high-efficiency power-clock generation techniques must be pursued to fully exploit the large computational energy efficiency of quasi-adiabatic logic in general and of DAMOS in particular.

Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultra-small-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte-Carlo simulator. These fluctuations are shown to pose fundamental barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation in multi-billion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard-maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40-600 mV, 10-100%, 2-20 mV/dec. and 10-10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V CMOS technology generation with 1.3-64 billion transistors on a chip. While these limits can be transcended to some degree by selecting optimal transistor width values larger than the channel length, the associated penalties in dynamic and static power, and in packing density demand novel MOSFET designs aimed at minimizing these fluctuations.