A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR systems, bitstream authentication is essential for avoiding fatal damage caused by unintended bitstreams. An encryption-only system can prevent bitstream cloning and reverse engineering, but cannot prevent erroneous or malicious bitstreams from being configured. Authenticated encryption is a relatively new concept that provides both message encryption and authentication, and AES-GCM is one of the latest authenticated encryption algorithms suitable for hardware implementation. We implemented the AES-GCM-based DPR system targeting the Virtex-5 device on an off-the-shelf board, and evaluated its throughput and hardware resource utilization. For comparison, we also implemented AES-CBC and SHA-256 modules on the same device. The experimental results showed that the AES-GCM-based system achieved higher throughput with less resource utilization than the AES/SHA-based system. The AES-GCM-module achieved more than 1 Gbps throughput and the entire system achieved about 800 Mbps throughput with reasonable resource utilization. This paper clarifies the advantage of using AES-GCM for protecting DPR systems.

We developed an FPGA-based content delivery system to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-Il Pro FPGA, the system provides a flexible single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played if and only if the downloaded circuit is correctly combined (= interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. In the present paper, we describe the detailed architecture of the proposed system and clarify the feasibility and effectiveness of this system experimentally using a single-chip partial reconfiguration. In addition, we discuss the fail-safe mechanisms, partially reconfigurable FPGA architecture, and future research necessary for the practical application of the system.

String matching circuits have been studied extensively for intrusion detection systems so far. An NFA-based string matching circuit, one of the works, has expandability of processing data width. However the resource requirement increases markedly, it was difficult to implement an NFA-based string matching circuit with whole the Snort 2.3.3 rule (35461 characters) that processes at 10 Gbps on a single FPGA. In this paper, the authors propose a highly efficient string matching circuit for FPGA. In our circuit, redundant AND-gates and states in the NFA are eliminated to reduce the resource requirement. Consequently, our circuit is reduced in the resources requirement by over 50% as compared with a previous NFA-based circuit, and the synthesis result shows that a string matching circuit that includes the whole Snort 2.3.3 rule can be implemented onto a single xc2vp-100-6 FPGA with throughput over 10 Gbps

A secure content distribution system is prototyped based on run-time partial reconfigurability of an FPGA. The system provides a robust content protection scheme for online content download services. The key idea is to divide the security module in a user terminal into Content-Specific Circuit (CSC) and Terminal Build-in Circuit (TBC) and to dynamically reconfigure CSC. CSC is customized for each content and transferred from a server in the form of encrypted configuration data. TBC is a uniquely identifiable processing unit that is combined with particular CSC to decrypt and decode contents. A content is properly decrypted and played by the security module only if its CSC is interlocked with the authorized TBC. To realize this CSC-TBC interlock authentication mechanism, partial reconfigurability of the FPGA is essential. This paper discusses the robustness and feasibility of the content distribution system through a proof-of-concept demonstration.

This paper proposes a method of generating a lightweight scalable NFA-based string matching circuit with elimination of redundant resources. String matching circuits have been studied extensively for intrusion detection systems. An NFA-based string matching circuit, one of the works, has expandability of the processing data width. Due to the huge hardware requirement, it was difficult to implement an NFA-based string matching circuit with the whole Snort 2.3.3 rule (35461 characters) that processes at 10 Gbps on a single FPGA. To reduce the circuit area, we eliminate redundant states of the NFA with the Aho-Corasick approach and redundant AND-gates in the NFA. Consequently, our method reduces the resource requirements by over 50% as compared with previous NFA-based circuits, and the synthesis result shows that a matching circuit that includes the whole Snort 2.3.3 rule can be implemented onto a single Xilinx Virtex-II pro xc2vp-100 with throughput over 10 Gbps

We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a client-server type on-line contents distribution services. The key component of this architecture is the digital content security circuit that is dynamically configured on the FPGA and performs the signal processing such as certification and decryption for replaying digital contents. The digital content security circuit is composed of two different circuits. One is the content-specific circuit that is built from the configuration data generated by the server. This circuit is specialized for each item of digital content. The other is the terminal built-in circuit that is uniquely programmed and implemented for each terminal, and is not open for the others. The content-specific circuit properly works only if it is combined with the terminal built-in circuit of the authorized client. We prototype and demonstrate a proof-of-concept model of the FPGA-based content protection system applicable to embedded consumer electronics such as set top boxes and cell phones.

High performance, low cost and compact specialized hardware for tsume-shogi (shogi problems) has been developed with a field-programmable gate array (FPGA). Developing dedicated hardware systems is an essential approach to improve the playing strength of shogi programs. However, inflexibility and high cost of hardware have been significant problems in development of the systems. An FPGA gives solutions to the problems of hardware implementation. To devise parallel and pipeline architecture of shogi hardware and test the feasibility of an FPGA for shogi, we first implemented a tsume-shogi solver. With the latest FPGA, we successfully implemented all of the highly parallelized modules on a single chip. The hardware tsume-shogi solver achieved about 11 times higher performance than software on Pentium4-2.53 GHz. The devised architecture can be also applied for normal shogi.

Imprecise computation is one of the promising schemes in real time systems to adapt the quality of computations to the change of load, keeping the deadlines of tasks in the systems. When overload occurs in the systems, the minimum requirements on the deadline are assured by decreasing the quality of the computation. This paper describes how to apply the concept of imprecise computation to automobile control in the expressway assuming the intelligent transportation system (ITS). The deadline violation of tasks for automobile control in the expressway induces collision of automobiles. Regardless of whether the expressway is congested or not, collision of automobiles must be avoided. To satisfy such requirement, the concept of imprecise computation is effective. This paper proposes a flexible scheduling using imprecise computation to avoid collision of automobiles and increase throughput.

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

The study deals with the automatic chamfering for the case of a machined hole on a cylinder on the basis of CAD data, using an industrial robot. As a chamfering tool, a rotary-bar driven by an electric motor is mounted to the arm of the robot having six degrees of freedom in order to give an arbitrary position and attitude to the tool. The robot control command converted from the chamfering path is transmitted directly to the robot. From the experimental results, the system is found effective to remove a burr along the edge of a hole on a cylindrical metallic workpiece.

The design and performance of a priority forwarding router chip are presented. The chip has four input and four output ports, employs clock-synchronized packet switching, and facilitates 32-bit priority arbitration by means of a priority forwarding scheme that prevents priority inversion and enables accurate priority control within a network. Packets are of a fixed size, each having three 38-bit segments. Each input port has an 8-packet priority queue that enables virtual cut-through switching and pipelined-simultaneous output to at most three different output ports. The chip has two 25-ns pipeline stages and its data transmission rate is 190 MByte/s per port. Clock level simulation shows that the chip can attain high throughput, 9 GByte/s and 34 GByte/s at 64-node and 256-node omega networks with random communication, and excellent real-time performance. Very small laxities are required for in-time delivery of all input packets where the packets exhibit a degree of deadline distribution.>

The authors propose a priority control scheme for packet switching multistage networks, called priority forwarding, which prevents priority inversion, a situation in which higher priority packets are blocked by lower priority packets. In an N*N omega network, the worst case delay of the priority forwarding scheme on the highest priority packet is O(log/sup 2/ N), while that for round-robin arbitration is O(N). Simulation results show that the priority forwarding scheme offers shorter delays for higher priority packets without throughput degradation and fits least-laxity-first control. The hardware implementation cost of this scheme is relatively small and requires no extra signal lines between routers. Consequently, this scheme offered predictability, scalability, and implementation eligibility.>

In this paper, a Lisp-based data-driven machine with a novel parallel control mechanism and its performance evaluation are presented. The proposed control mechanism is the natural extension of a data-driven scheme to function evaluation and is achieved by packet communication architecture. First, the organization of the data-driven machine is described and, then the results of the simulation studies are shown which confirm the effectiveness of the control mechanism. The performance characteristics of the data-driven machine obtained by the software simulator are also given.