Presents a novel feed-through assignment algorithm based on minimum-cost multi-commodity flow formulation. After finding single-commodity flow with flow conflicts on the formulation, the algorithm eliminates all the conflicts to obtain a feasible solution. Since all nets and cell rows are considered simultaneously, our algorithm globally minimizes the number of tracks, the wire length, and the number of vias. Experimental results on benchmarks show that our algorithm substantially reduces these numbers compared with conventional algorithms.

VLSI chips for luminance/chrominance (Y/C) signal separation and synthesis have been developed. Application-specific FIR filter structures and canonical signed-digit representation (CSR) multipliers used in the filters make it possible to develop compact high-speed VLSI chips. A silicon compiler, which employs the optimal FIR filter structures and supplies the optimal filter design faculty, has contributed to quick VLSI development. Y/C signal separation using four video FIR filters and Y/C signal synthesis using three video FIR filters are implemented on single chips by 1.2- mu m CMOS technology.>

The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm*11.7-mm die size and attains about 860-MOPS operating speed.>

This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.