Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Vasu Singh

dblp:97/4322 · DBLP profile ↗
← Back
17ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0002-7886-6464ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 7 · 1 first-author · 2 since 2021Systems, architecture and hardware · 5 · 1 since 2021Theory of computation · 5 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Hardware accelerators and domain-specific architectures · 70% Embedded and real-time systems · 18% Memory systems · 7%
Software engineering, system software, and programming languages
4 papers
Compilers and program optimization · 60% Concurrent programming · 22% Program verification · 18%
Artificial intelligence
1 paper
Autonomous driving · 100%

Topics — the 16 heaviest of 19, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
verified compilation
1.012026
Ensuring Safety in Automotive Machine Learning Inference: From Pre-validated Static Kernels to Machine Learning Graph Compilation · CAV (3) 2026
Hardware accelerators and domain-specific architectures
kernel generation
1.012026
Ensuring Safety in Automotive Machine Learning Inference: From Pre-validated Static Kernels to Machine Learning Graph Compilation · CAV (3) 2026
Hardware accelerators and domain-specific architectures
machine learning accelerator
1.012026
Ensuring Safety in Automotive Machine Learning Inference: From Pre-validated Static Kernels to Machine Learning Graph Compilation · CAV (3) 2026
Robotics › Autonomous driving
perception
0.612022
Zhuyi: perception processing rate estimation for safety in autonomous vehicles · DAC 2022
Program verification › security property verification
memory safety verification
0.312026
Ensuring Safety in Automotive Machine Learning Inference: From Pre-validated Static Kernels to Machine Learning Graph Compilation · CAV (3) 2026
Concurrent programming
transactional memory
0.222009
Preventing versus curing: avoiding conflicts in transactional memories · PODC 2009
Software Transactional Memory on Relaxed Memory Models · CAV 2009
Parallel and multicore computing
parallel scheduling
0.112011
Scheduling large jobs by abstraction refinement · EuroSys 2011
Concurrent programming › transactional memory
software transactional memory
0.112009
Software Transactional Memory on Relaxed Memory Models · CAV 2009
Memory systems › memory consistency
memory consistency model
0.112009
Software Transactional Memory on Relaxed Memory Models · CAV 2009
Memory systems › memory consistency › memory consistency model
weak memory model
0.112009
Software Transactional Memory on Relaxed Memory Models · CAV 2009
Automated reasoning and model checking
model checking
0.112008
Model checking transactional memories · PLDI 2008
Automated reasoning and model checking
synthesis
0.112007
Algorithms for Interface Synthesis · CAV 2007
Cloud and datacenter computing
cluster resource management and scheduling
0.012011
Scheduling large jobs by abstraction refinement · EuroSys 2011
Embedded and real-time systems
real-time scheduling
0.012011
Scheduling large jobs by abstraction refinement · EuroSys 2011
Concurrent programming
memory models
0.012009
Software Transactional Memory on Relaxed Memory Models · CAV 2009
Concurrent programming › memory models
weak memory models
0.012009
Software Transactional Memory on Relaxed Memory Models · CAV 2009

Methods — techniques the papers use, named apart from their topics

formal methods · 2.0MLIR · 2.0AI-driven testing · 2.0frame processing rate estimation · 1.1model checking · 0.2finite-state reduction · 0.2abstraction refinement · 0.1contention manager · 0.1access set prediction · 0.1
YearPublicationVenuePosition
2026 Ensuring Safety in Automotive Machine Learning Inference: From Pre-validated Static Kernels to Machine Learning Graph Compilation
abstract
Abstract Machine Learning (ML) inference is shifting from using pre-developed static, CUDA C++, GPU kernel libraries to using MLIR-based graph compilers that perform advanced optimizations and generate custom kernels. This paradigm shift reimagines how we achieve ML inference in safety-critical domains such as automotive applications. Traditional approaches relied on qualifying static kernel libraries—pre-built for fixed input shapes and parameter ranges—according to the ISO 26262 standard. However, the demanding performance requirements of diverse ML models and rapidly evolving hardware accelerators necessitate generating optimized kernels on the fly, which only ML graph compilers can provide. This paper presents an industrial experience report on a comprehensive verification framework for ML inference in automotive applications. We describe the transition from static kernels to dynamic ML graph compilation and introduce two complementary verification strategies: (1) formal methods targeting memory safety and concurrency properties in CUDA kernels and MLIR-based compiler; and (2) AI-driven testing for functional correctness. Our experience over multiple years of production use demonstrates that validating ML graph compiler output can satisfy the ISO 26262 ASIL B requirements - without requiring compiler tool qualification - while enabling performance and flexibility benefits. We discuss remaining challenges including scalability of formal verification and adapting to evolving compilers and hardware platforms.
Jelena Frtunikj, Alex Latz, Ajit Mistry, Matthew Propp, Vasu Singh, Suresh Talapaneni, Amanda Tang, Damien Zufferey
CAV (3)5
2025 Alignment Monitoring
Thomas A. Henzinger, Konstantin Kueffner, Vasu Singh, I Sun
RV3
2022 Zhuyi: perception processing rate estimation for safety in autonomous vehicles
abstract
The processing requirement of autonomous vehicles (AVs) for high-accuracy perception in complex scenarios can exceed the resources offered by the in-vehicle computer, degrading safety and comfort. This paper proposes a sensor frame processing rate (FPR) estimation model, Zhuyi, that quantifies the minimum safe FPR continuously in a driving scenario. Zhuyi can be employed post-deployment as an online safety check and to prioritize work. Experiments conducted using a multi-camera state-of-the-art industry AV system show that Zhuyi's estimated FPRs are conservative, yet the system can maintain safety by processing only 36% or fewer frames compared to a default 30-FPR system in the tested scenarios.
Yu-Shun Hsiao, Siva Kumar Sastry Hari, Michal Filipiuk, Timothy Tsai 0002, Michael B. Sullivan 0001, Vijay Janapa Reddi, Vasu Singh, Stephen W. Keckler
DAC7
2011 Scheduling large jobs by abstraction refinement
abstract
The static scheduling problem often arises as a fundamental problem in real-time systems and grid computing. We consider the problem of statically scheduling a large job expressed as a task graph on a large number of computing nodes, such as a data center.
Thomas A. Henzinger, Vasu Singh, Thomas Wies, Damien Zufferey
EuroSys2
2011 Verification of STM on relaxed memory models
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
Formal Methods Syst. Des.3
2010 FlexPRICE: Flexible Provisioning of Resources in a Cloud Environment
abstract
Cloud computing aims to give users virtually unlimited pay-per-use computing resources without the burden of managing the underlying infrastructure. We claim that, in order to realize the full potential of cloud computing, the user must be presented with a pricing model that offers flexibility at the requirements level, such as a choice between different degrees of execution speed and the cloud provider must be presented with a programming model that offers flexibility at the execution level, such as a choice between different scheduling policies. In such a flexible framework, with each job, the user purchases a virtual computer with the desired speed and cost characteristics, and the cloud provider can optimize the utilization of resources across a stream of jobs from different users. We designed a flexible framework to test our hypothesis, which is called FlexPRICE (Flexible Provisioning of Resources in a Cloud Environment) and works as follows. A user presents a job to the cloud. The cloud finds different schedules to execute the job and presents a set of quotes to the user in terms of price and duration for the execution. The user then chooses a particular quote and the cloud is obliged to execute the job according to the chosen quote. FlexPRICE thus hides the complexity of the actual scheduling decisions from the user, but still provides enough flexibility to meet the users actual demands. We implemented FlexPRICE in a simulator called PRICES that allows us to experiment with our framework. We observe that FlexPRICE provides a wide range of execution options-from fast and expensive to slow and cheap-- for the whole spectrum of data-intensive and computation-intensive jobs. We also observe that the set of quotes computed by FlexPRICE do not vary as the number of simultaneous jobs increases.
Thomas A. Henzinger, Anmol V. Singh, Vasu Singh, Thomas Wies, Damien Zufferey
IEEE CLOUD3
2010 Verifying Local Transformations on Relaxed Memory Models
Sebastian Burckhardt, Madan Musuvathi, Vasu Singh
CC3
2010 A marketplace for cloud resources
abstract
Cloud computing is an emerging paradigm aimed to offer users pay-per-use computing resources, while leaving the burden of managing the computing infrastructure to the cloud provider. We present a new programming and pricing model that gives the cloud user the flexibility of trading execution speed and price on a per-job basis. We discuss the scheduling and resource management challenges for the cloud provider that arise in the implementation of this model. We argue that techniques from real-time and embedded software can be useful in this context. Categories and Subject Descriptors
Thomas A. Henzinger, Anmol V. Singh, Vasu Singh, Thomas Wies, Damien Zufferey
EMSOFT3
2010 Runtime Verification for Software Transactional Memories
Vasu Singh
RV1
2010 Transactions in the jungle
abstract
Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of TM executions have been proposed. Many of these definitions assumed that accesses to shared data are solely performed through transactions. In practice, due to legacy code and concurrency libraries, transactions in a TM have to share data with non-transactional operations. The semantics of such interaction, while widely discussed by practitioners, lacks a clear formal specification. Those interactions can vary, sometimes in subtle ways, between TM implementations and underlying memory models.
Rachid Guerraoui, Thomas A. Henzinger, Michal Kapalka, Vasu Singh
SPAA4
2010 Model checking transactional memories
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
Distributed Comput.3
2009 Software Transactional Memory on Relaxed Memory Models
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
CAV3
2009 Preventing versus curing: avoiding conflicts in transactional memories
abstract
Transactional memories are typically speculative and rely on contention managers to cure conflicts. This paper explores a complementary approach that prevents conflicts by scheduling transactions according to predictions on their access sets.
Aleksandar Dragojevic, Rachid Guerraoui, Anmol V. Singh, Vasu Singh
PODC4
2008 Completeness and Nondeterminism in Model Checking Transactional Memories
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
CONCUR3
2008 Model checking transactional memories
abstract
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memory. We show that, under certain conditions, the verification problem can be reduced to a finite-state problem, and we illustrate the use of the method by proving the correctness of several STMs, including two-phase locking, DSTM, TL2, and optimistic concurrency control. The safety properties we consider include strict serializability and opacity; the liveness properties include obstruction freedom, livelock freedom, and wait freedom.
Rachid Guerraoui, Thomas A. Henzinger, Barbara Jobstmann, Vasu Singh
PLDI4
2008 Permissiveness in Transactional Memories
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
DISC3
2007 Algorithms for Interface Synthesis
Dirk Beyer 0001, Thomas A. Henzinger, Vasu Singh
CAV3