How to defend against attacks in Federated Partial Label Learning (FedPLL) is a brand new and challenging question in machine learning security due to stealthy and efficient attack behaviors of adversaries. In this paper, we systematically study this problem by developing an Adaptive Partial Label Attack (APLA) which subtly manipulates the candidate label set of the data sample. To defend against APLA, we develop the RobustFedPLL framework incorporating three modules: (1) in preliminary clustering, we implement a Gaussian Mixture Model (GMM) and a moving average mechanism to identify clients' confidence; (2) in representation contrasting, we develop a contrast-based algorithm to obtain clients' model feature representations; (3) in final clustering, we utilize mainstream clustering algorithms to finally distinguish adversaries. Experiments of RobustFedPLL and SOTA defense algorithms based on two datasets are conducted, demonstrating the superiority of RobustFedPLL under various experimental settings.

In this brief, a high-gain and wide-bandwidth single-stage gain-boosted cascode amplifier (GBCA) is proposed for the front-end sample-and-hold amplifier (SHA) in 14-bit 2.5-GS/s pipelined analog-to-digital converter (ADC). This GBCA is composed of a two-layer main cascode amplifier and a three-layer cascode feedback amplifier (FA). The three-layer cascode structure introduces more than 20-dB gain enhancement compared with conventional two-layer FAs. However, adjacent poles appear near the gain bandwidth product (GBW) of the three-layer cascode FA, which may seriously deteriorate the phase margin (PM) of the FA and further prolong the settling time of closed-loop GBCA. A PM expansion technique is proposed to improve the PM of FA by adding a group of switched capacitor array. At the same time, the open-loop GBCA achieves 104-dB direct-current (dc) gain and 65.2-GHz GBW, which satisfies the harsh requirements of the ping-pong interleaved SHA with 12-dB gain on-chip. The pipelined ADC fabricated in 28-nm CMOS process consumes 554 mW at 2.5-GS/s sampling rate, while achieves a signal-to-noise-and-distortion ratio (SNDR) of 52.5 dB and a spurious free dynamic range (SFDR) of 86.4 dBc with 161-MHz input signal.

This paper studies the design of a key-value (KV) store that can take full advantage of modern storage hardware with built-in transparent compression capability. Many modern storage appliances/drives implement hardware-based data compression, transparent to OS and applications. Moreover, the growing deployment of hardware-based compression in Cloud infrastructure leads to the imminent arrival of Cloud-based storage hardware with built-in transparent compression. By decoupling the logical storage space utilization efficiency from the true physical storage usage, transparent compression allows data management software to purposely waste logical storage space in return for simpler data structures and algorithms, leading to lower implementation complexity and higher performance. This work proposes a table-less hash-based KV store, where the basic idea is to hash the key space directly onto the logical storage space without using a hash table at all. With a substantially simplified data structure, this approach is subject to significant logical storage space under-utilization, which can be seamlessly mitigated by storage hardware with transparent compression. This paper presents the basic KV store architecture, and develops mathematical formulations to assist its configuration and analysis. We implemented such a KV store KallaxDB and carried out experiments on a commercial SSD with built-in transparent compression. The results show that, while consuming very little memory resource, it compares favorably with the other modern KV stores in terms of throughput, latency, and CPU usage.

This paper studies utilizing the growing family of solid-state drives (SSDs) with built-in transparent compression to simplify the data structure of cache design. Such storage hardware allows the user applications to intentionally under-utilize logical storage space (i.e., sparse LBA utilization, and sparse storage block content) without sacrificing the physical storage space. Accordingly, this work proposed an index-less cache management approach to largely simplify the flash-based cache management by leveraging SSDs with built-in transparent compression. We carried out various experiments to evaluate the write amplification and read performance of the proposed cache management, and the results show that our proposed indexless cache management can achieve comparable or much better performance than the conventional policies while consuming much less host computing and memory resources.

This paper presents an approach to enable relational database take full advantage of modern storage hardware with built-in transparent compression. Advanced storage appliances (e.g., all-flash array) and some latest SSDs (solid-state drives) can perform hardware-based data compression, transparently from OS and applications. Moreover, the growing deployment of hardware-based compression capability in Cloud storage infrastructure leads to the imminent arrival of cloud-based storage hardware with built-in transparent compression. To make relational database better leverage modern storage hardware, we propose to deploy a dual in-memory vs. on-storage page format: While pages in database cache memory retain the conventional row-based format, each page on storage devices has a column-based format so that it can be better compressed by storage hardware. We present design techniques that can further improve the on-storage page data compressibility through additional light-weight column data transformation. We the impact of compression algorithms on the selection of column data transformation techniques. We integrated the design techniques into MySQL/InnoDB by adding only about 600 lines of code, and ran Sysbench OLTP workloads on a commercial SSD with built-in transparent compression. The results show that the proposed solution can bring up to 45% additional reduction on the storage cost at only a few percentage of performance degradation.

This paper presents a design framework aiming to mitigate occasional HDD fail-slow. Due to their mechanical nature, HDDs may occasionally suffer from spikes of abnormally high internal read retry rates, leading to temporarily significant degradation of speed (especially the read latency). Intuitively, one could expect that existing system-level data redundancy (e.g., RAID or distributed erasure coding) may be opportunistically utilized to mitigate HDD fail-slow. Nevertheless, current practice tends to use system-level redundancy merely as a safety net, i.e., reconstruct data sectors via system-level redundancy only after the costly intra-HDD read retry fails. This paper shows that one could much more effectively mitigate occasional HDD fail-slow by more pro-actively utilizing existing system-level data redundancy, in complement to (or even replacement of) intra-HDD read retry. To enable this, HDDs should support a higher degree of controllability and observability in terms of their internal read retry operations. Assuming a very simple form enhanced HDD controllability and observability, this paper presents design solutions and a mathematical formulation framework to facilitate the practical implementation of such pro-active strategy for mitigating occasional HDD fail-slow. Using RAID as a test vehicle, our experimental results show that the proposed design solutions can effectively mitigate the RAID read latency degradation even when HDDs suffer from read retry rates as high as 1% or 2%.

To mitigate the long write latency of NAND flash memory, solid-state drives (SSDs) typically use capacitor-powered SRAM or DRAM to realize internal nonvolatile write buffering. Due to the cost and size constraints, intra-SSD capacitors can only power a very small amount (e.g., 8 MB or 16 MB) of nonvolatile write buffer. As a result, most commercial SSDs simply use the few MBs of capacitor-powered write buffer in the first-in first-out (FIFO) manner without employing any advanced data eviction policy. This paper presents a set of design strategies across the application and storage device levels that can effectively leverage the very small intra-SSD write buffer to noticeably reduce the amount of data being physically written to NAND flash memory. These cross-layer design strategies are primarily geared towards mainstream applications (e.g., database and filesystem) that heavily involve logging/journaling operations. This paper discusses different strategies for realizing flash memory write traffic reduction through nominal application-level modifications, and presents solutions to accordingly manage the write buffer at small processing and memory resource usage inside SSDs. To evaluate the potential effectiveness, we carried out case studies based upon popular open-source relational databases and filesystem. With only 8 MB of intra-SSD capacitor-powered write buffer, our experimental results show that the developed design solutions can reduce up to 39.7, 36.5, and 52.9 percent of total NAND flash memory write traffic for MySQL, ext4, and PostgreSQL, respectively.

This article presents a design framework aiming to reduce mass data storage cost in data centers. Its underlying principle is simple: Assume one may noticeably reduce the HDD manufacturing cost by significantly (i.e., at least several orders of magnitude) relaxing raw HDD reliability, which ensures the eventual data storage integrity via low-cost system-level redundancy. This is called system-assisted HDD bit cost reduction. To better utilize both capacity and random IOPS of HDDs, it is desirable to mix data with complementary requirements on capacity and random IOPS in each HDD. Nevertheless, different capacity and random IOPS requirements may demand different raw HDD reliability vs. bit cost trade-offs and hence different forms of system-assisted bit cost reduction. This article presents a software-centric design framework to realize data-adaptive system-assisted bit cost reduction for data center HDDs. Implementation is solely handled by the filesystem and demands only minor change of the error correction coding (ECC) module inside HDDs. Hence, it is completely transparent to all the other components in the software stack (e.g., applications, OS kernel, and drivers) and keeps fundamental HDD design practice (e.g., firmware, media, head, and servo) intact. We carried out analysis and experiments to evaluate its implementation feasibility and effectiveness. We integrated the design techniques into ext4 to further quantitatively measure its impact on system speed performance.

Having the unique feature of wide continuous bandwidth, millimeter-wave communication has attracted great attention from both industry and academics. However, due to the large path loss and diffraction loss, human body shadowing (HBS) has a huge impact on millimeter- wave communication and requires intensive research. In this paper, we conduct HBS measurements in three different cases at 28 GHz by using a pair of horn antennas. Based on our measurement results, we propose a simple HBS model, and then use the double-edge and the multiple-edge diffraction method to study the characteristics of HBS. The gain of HBS is generally 10 dB or greater for the 16 m LOS link. It grows with the distance between TX and RX, and a relative small gain will be obtained when people are close to the antennas and LOS path. Furthermore, human body's direction will have great impact on the effective height, which finally causes 4.63 dB loss.

A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.

This paper presents an area efficient decoder architecture that supports both perfectly structured and not perfectly structured LDPC codes. To verify our architecture, an area-efficient LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed. A solution is proposed to avoid memory access conflict problem caused by TDMP algorithm. The main timing schedule is arranged carefully to handle the operations of our solution while avoiding much additional hardware consumption. We also optimize the extrinsic message storing strategy to reduce the memory bits needed. Besides the extrinsic message recover and the accumulate operation are merged together. Based on SMIC 0.13 um standard CMOS process, the core area of the decoder is only 4.75 mm2and the maximum operating clock frequency is 200 MHz. With 5 iterations, the estimated average power consumption is 48.4 mW at 25 MHz for CMMB and 130.9 mW at 50 MHz for DTMB with 1.2V supply.

In this paper, taking the channel estimation error (CEE) and noise into consideration, an analytical expression for envelope correlation coefficient (ECC) of the maximal ratio combining (MRC) output has been obtained in correlated Rician fading environments in the high signal-to-noise ratio (SNR) region, which provides a deep insight into the impacts of CEE, noise, frequency separation, Rician factor and channel attenuation, etc. Besides, we found that the ECC can be used to predict system performance such as average channel capacity and outage probability quantitatively in the identical statistical characteristic environment.

In this paper, a multi-user multiple input multiple output (MIMO) system using semi-orthogonal space division multiplexing (semi-OSDM) and single-user QR-triangular detection with Alamouti code is studied. In this proposed semi-OSDM with STBC system, the transmit signals for each user are grouped into pairs and separately coded by using the standard Alamouti space-time code, while QR decomposition is used to make the signaling streams triangular so that the serial interference cancellation (SIC) can be utilized to maintain an accurate signal detection at the receiver. The bit error rate (BER) performance of the proposed semi-OSDM with STBC system outperforms the orthogonal space division multiplexing (OSDM) system as well as the semi-OSDM system, while exploiting a reduced complexity and stability when the correlation of the channel changes. Moreover, it largely reduces the complexity of the receivers.

In this paper, we provide some exact expressions in a close form for central moment envelope correlation coefficient (ECC) and joint moment ECC of the maximal ratio combining (MRC) output in correlated Rayleigh and Rician fading environments. Besides, we deduce an analytical formula for average capacity with minor approximation. With these expressions, a simple relationship between joint moment ECC and the average capacity is presented, which means that only joint moment ECC can be used to predict system performance such as average channel capacity quantitatively. Furthermore, it has been demonstrated by Monte Carlo simulation that our analysis are matched with the numerical results excellently.

This work investigates a design of minimizing the system outage probability adaptive modulation algorithm in the downlink of the multi-user multiple-input multiple-output (MIMO) system. Based on a beamforming scheme that maximizes the signal-to-leakage ratio (SLR), this new algorithm is proposed for constant bit rate services to maximize the number of satisfied users and minimize the transmission power. Furthermore, this proposed algorithm has advantage in the system spectral efficiency.

In this paper, with minor approximation, we provide analytical expressions in a close form for the envelope correlation coefficient (ECC) and outage probability of the maximal ratio combining (MRC) output in correlated Rayleigh and Rician fading environments. Moreover, we find a simple relationship between ECC and the outage probability, which indicates that ECC can be used to predict system performance such as outage probability quantitatively. Besides, it has been demonstrated by Monte Carlo simulation that our analysis are matched with the numerical results excellently.