The most computation intensive step in video encoding is motion estimation which determines the translational motion (motion vector) of pixel blocks across two or more pictures. Traditional fast techniques for blockmatching motion estimation aim only at reducing the number of locations to check, but not the amount of computation to do at each of these check locations. This paper presents a heuristic-based motion estimation technique which reduces both the number of search locations (via subsampling) as well as the number of operations to perform at each search location (via simplified signature), thus achieving a high speedup factor. Test results show that quality of the motion vectors found by this heuristic-based technique is close to that of full-search motion vectors.

Hi-PASS, a CAD system for digital signal processor (DSP) architecture synthesis, has been developed to automatically produce maximally parallel VLSI designs for real-time applications. The target DSP applications are the class for which desired sample rates are so high that time sharing of hardware is not feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design which can be fabricated using standard cells provided by the Lager IV silicon assembly system. Hi-PASS is a collection of modular tools, several of which contain new techniques within the field of synthesis. C code is converted into a flowgraph using a technique known as symbolic interpretation, including new methods for handling certain types of input-dependent control flow. The HOPS program is a heuristic search flowgraph optimizer tailored for the arithmetic intensive structures necessary for real-time DSP applications. The high throughput rates necessary for these applications also require that retiming be used to provide very short inter-register delay times. A new retiming tool has been developed which allows for computationally efficient bit-level retiming.>

This work deals with the general case of processors with multiple, possibly pipelined, functional units that operate concurrently and presents a method for the minimization of the actual computation time n/sub sys/*t/sub sys/. The selection of a linear scheduling function, which minimizes n/sub sys/*t/sub sys /is formulated as a combinatorial optimization problem, which is shown to have a bounded search space. An efficient branch-and-bound method for the solution of that problem is proposed and applied to several examples.>

One of the crucial steps in designing VLSI circuits is to verify the correctness of the layout of the circuitry. Traditionally, this verification step is done by first flattering out the circuit hierarchy. This approach requires a substantial amount of computational overhead even for circuits that are relatively small. In this paper, a connectivity verification algorithm which exploits circuit hierarchy is presented. This algorithm works most efficiently with big circuits and is therefore useful for verifying VLSI circuits.