EDBT 2026 Demo / reviewers in the wild / expert
P. I. Jennings
dblp:97/555
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1984
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Integrated circuit design · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › ASIC design
gate array |
0.0 | 1 | 1984 | A Highly Routable ULM Gate Array and Its Automated Customizaton · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984 |
Electronic design automation › physical design › placement and routing
gate array placement and routing |
0.0 | 1 | 1984 | A Highly Routable ULM Gate Array and Its Automated Customizaton · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984 |
Electronic design automation
physical design |
0.0 | 1 | 1984 | A Highly Routable ULM Gate Array and Its Automated Customizaton · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984 |
Methods — techniques the papers use, named apart from their topics
structured interconnection topology · 0.0automated customization software · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1984 | A Highly Routable ULM Gate Array and Its Automated CustomizatonabstractThis paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing. Emphasis is placed upon the considerations which influence the selection of a functional array primitive. A highly structured interconnection architecture will be described, which employs interdigitating cell terminals in a polycell-like wiring channel topology to simplify the routing procedure for the array. The detailed structure and operation of an automatic customization software package is discussed. This package, developed specially for the array, utilizes the structured topology to achieve track densities which are comparable with those produced by state-of-the-art algorithms. This array has been fabricated, in a CMOS technology, as a test-vehicle for both the unusual topology and the unique functional cells. Throughout the study, emphasis has been placed on achieving a coherent strategy for producing efficiently routed gate-arrays with the minimum of sophisticated design tools. Examples will be cited to show that this methodology is economical both in the rapidity with which finished designs may be produced, and in its utilization of silicon-area. P. I. Jennings, Stanley L. Hurst, A. McDonald |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |