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Terry Tateyama

dblp:97/6173 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 92% High-performance computing · 8%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management
address remapping
0.011999
Impulse: Building a Smarter Memory Controller · HPCA 1999
Memory systems
memory controller
0.011999
Impulse: Building a Smarter Memory Controller · HPCA 1999
Memory systems › cache
prefetching
0.011999
Impulse: Building a Smarter Memory Controller · HPCA 1999
Memory systems
memory-bound computation
0.011999
Impulse: Building a Smarter Memory Controller · HPCA 1999
High-performance computing
scientific computing
0.011999
Impulse: Building a Smarter Memory Controller · HPCA 1999

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1999 Impulse: Building a Smarter Memory Controller
abstract
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang 0002, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Terry Tateyama
HPCA12