Processing using memory (PuM) leverages analog properties of memory infrastructure to implement logic and arithmetic operations. Commodity Off-The-Shelf (COTS) DRAM is particularly attractive for PuM because it requires no device modification, thereby preserving the ubiquity, availability, and cost advantages of modern DRAM while enabling massive column-level parallelism. We propose CADM (Content-Addressable DRAM), that enables exact and approximate (similarity) search in- and using- unmodified COTS DRAM. CADM targets genome classification, which is one of the most important applications in bioinformatics. Specifically, rapid and accurate detection of bacterial pathogens is critical for effective clinical decision-making, particularly in life-threatening conditions such as sepsis, where early identification of the causative agent significantly improves patient outcomes. We implement CADM in commercial DDR4 and show that it can achieve up to 185 × higher throughput and 73 × energy savings compared to CPU-run state-of-the-art classifier Kraken2. Using approximate search, CADM can achieve 9 × higher F 1 score when matching relatively short ( < 32 DNA bases) ambiguous and erroneous k -mers.

Iontronics is a potential approach to expand electronic circuit capabilities by using ions as charge carriers to perform computation. This live demonstration showcases the integration of logic gates made from bipolar polyelectrolyte diodes on a printed circuit board (PCB), powered and controlled by a standard microcontroller. Visitors can interact with the iontronic circuit through a simple user interface, setting inputs and observing real-time outputs. Participants will also inject various solutions into the iontronic chip, allowing them to explore how changes in solution properties, such as ionic conductivity, affect circuit performance.

We propose a novel resistive edit distance-tolerant content addressable memory for computational genomics applications, particularly for detection and identification of pathogens of pandemic importance. Unlike state-of-the-art approximate search solutions that tolerate small number of replacements between the query pattern and the stored data, DIPER tolerates insertions and deletions, ubiquitous in genomics. DIPER achieves up to 1.7× higherF1score for high-quality DNA reads and up to 6.2× higherF1score for DNA reads with 15% error rate, compared to state-of-the-art DNA classification tool Kraken2. Simulated at 500MHz, DIPER provides 910× average speedup over Kraken2.

Dynamic logic is a high-speed technology that was previously used in mature technologies, but lost popularity due to the increased leakage and process variations in advanced technologies. However, the recent popularity of circuits running in the cryogenic region provides a new opportunity for dynamic operation, thanks to the reduced leakages at such low temperatures. This paper revisits dynamic logic as a true candidate for high-performance and energy-efficient circuits for cryogenic operation in nanoscaled technologies. The paper first overviews and analyzes transistor operation at cryogenic temperatures and how it influences digital circuit design targeted to this regime. With these effects in mind, the use of dynamic logic families, including the classical dynamic (NORA) logic and the recently introduced Dual Mode Logic (DML) and Dual Mode Pass Logic (DMPL) families, are examined under cryogenic operation, showcasing improved performance and power efficiency. Measurements conducted on a 16 nm FinFET test chip validate their operation at low temperatures down to 4K, with supply voltages ranging 0.4–0.8-V. Furthermore, the considered dual mode logic families exhibit performance enhancements of up to 26% in dynamic mode and power efficiency increases up to 53% in static mode, compared to CMOS.

This Special Issue of IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS). This annual symposium provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. The symposium is a space where the Circuits and Systems (CAS) community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields. The 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023) was held in person from February 28 to March 3 in Quito, Ecuador. A subset of top-rated papers was selected for this Special Issue among all the contributions presented at the conference in poster and oral sessions. The invited papers brought new technical results and underwent a peer-review process consisting of expert reviewers on the related topics. A brief description of the two selected papers is as follows.

PUF circuits utilize multiple identical bit-cells to generate their unique keys. Thus, the Si area of each bit has a profound impact on the circuit. A method for extraction of multiple independent bits from single PUF cells is proposed. This method utilizes PUF preselection ‘tilt’ tests to obtain a new, uncorrelated, entropy source. During tilt tests, intentional controllable mismatch is introduced to the PUF cells, and their stability is concluded. The test could be revisited as a method to measure the internal mismatch size, by finding the tilt size required to flip the test result from ‘pass’ to ‘fail’. As the mismatch size is random and uncorrelated, it could be used to extract multiple additional PUF bits, as well as to find the unstable bit-cells relative to each new PUF bit. A Si implementation, which relies on the capacitive tilt PUF, in TSMC 65nm, is presented, with two additional bits. This demonstrates the applicability of the scheme for multiple new bits. Measured results of the second new bit show BER of 4E-4, zero additional cell area and excellent uniqueness and randomness.

Dual Mode Logic (DML) enables the dynamical operation of digital circuits optimized for energy-delay efficiency. Here, for the first time, DML is examined under cryogenic conditions, and its characteristics are evaluated for future applications. As a proof-of-concept, a DML testchip designed in 65nm technology was measured under cryogenic temperatures down to 4K. Measurements at supply voltages from 0.8V to 1.2V and temperatures ranging from 300K (room temperature) to 4K, confirm the effectiveness of DML under extreme temperatures.

The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16×16-bit Booth multiplier fabricated as a part of an ultra-low power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same design saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from - 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.

The emergence of autonomous applications, vision and information systems, and the shift from charge coupled devices (CCD) to complementary metal oxide silicon (CMOS) have led to significant advances in the image sensing field by extending research and development of new devices to the 3D sensing and neuromorphic functions field. We present a new weight-based operating concept for the current assisted photonic demodulator (CAPD) device and show how it can be used in future neuromorphic sensors. The new photodiode is capable of variably dividing the photo-generated charges amongst the surrounding pixels as well as real-time feed-backing between neighboring pixels. TCAD simulations are performed and analyzed to verify the new design's feasibility. A customized pixel circuit and pixel array which support the new photodiode design and operation concept are proposed as well as setups for averaging and edge detection functionalities.

In the past, Pass Transistor Logic (PTL) was widely used due to benefits in terms of speed and power consumption coming from the reduced number of transistors. However, issues such as threshold drop across the single-channel pass transistors and high sensitivity to process variations have prevented the use of PTL in advanced nanometer technologies. In this paper, we propose a novel logic family named Dual Mode Pass Logic (DMPL), which allows for high speed and low power consumption while maintaining robustness down to the sub-threshold voltage region. The DMPL effectively combines PTL to reduce energy and power consumption along with the flexibility of Dual Mode Logic (DML) to switch to a speed improved operating mode according to the system requirement. Simulation analysis performed on basic NOR/NAND gates implemented in 16 nm Finfet technology demonstrates that DMPL can reduce energy and power by 33% and 42% as compared to logically equivalent static CMOS design. Moreover, running frequency of a DMPL circuit can exceed that of its static CMOS counterpart by 84% when speed is mandatory. Additionally, DMPL gates demonstrate similar robustness as static CMOS implementations under process and temperature variations at lower supply voltages.

In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (E-D) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.

Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

Side channel analysis attacks are considered an extreme hardware security hazard for cryptographic devices. There are numerous approaches to prevent attackers from extracting useful information from secured devices. Nonetheless the cost of implementing an effective countermeasure is usually very high in terms of area/performance. In this paper we propose a novel approach to the temporal redistribution of the power information. Specifically, we present a circuit level methodology that makes it possible to manipulate the three main parameters of the current profile during the clock period: the start time of the computation, the duration and the amplitude. The effectiveness of the proposed countermeasure was evaluated on a 4-bit cryptographic function in a 65nm TSMC process. The simulation results indicate that the number of secret bits that leaked from the protected design (i.e., the mutual information) was reduced dramatically from 4 bits to 0.85 bits. In addition, at least 1500 ideal noise-free power traces were required to extract these bits, whereas less than 150 traces were required to extract the whole 4 bits from the unprotected design. The sensitivity of the protected circuit to process and environmental variations are minimal, with measured standard deviation of 0.1bit. The area overhead is up to 32%.

An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2per bit.

The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-adjustment mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (-35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.

Information leakage through physical channels is a major hurdle in embedded hardware security. This paper overviews the three key factors in the embedded hardware security space, focusing on gray-box (bounded resources) power analysis attacks: the adversary's knowledge and abilities, the security metrics used by adversaries' and security evaluators and gate-level countermeasures. A new design paradigm, dubbed pAsynch, that utilizes internal signals and random signals to uniformly spread the information-carrying energy within the clock period in a specific way with a resolution below the band-width and noise-filtering abilities of advanced measurement equipment is introduced. The advantages and design challenges introduced by the pAsynch paradigm are discussed.

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. However, the emerging approximate computing paradigm utilizes the inherent error resilience of some applications to tolerate data errors. Such error tolerance can be exploited by reducing the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption, at the cost of an increase in cell failure probability. In this demonstration, we present the first fabricated and fully functional GC-eDRAM in a 28 nm bulk CMOS technology. The array, which is based on a novel mixed-VT 4T bitcell, can be used in both traditional and for approximate computing applications, featuring a small silicon footprint and supporting high-performance operation. Silicon measurements demonstrate successful operation at 800 Mhz under a 900 mV supply, while retaining almost 30% lower area than a single-ported 6T SRAM in the same technology.

Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and data-dependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.

For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technology, with the goal of improving energy efficiency for wide supply voltage operation range. By combining the operating characteristics of the DML and the extended body bias capability of the technology, energy efficient digital circuits that can effectively benefit from adaptive voltage and frequency scaling techniques can be defined. This manuscript reports evaluations of the DML against conventional static and dynamic CMOS logics for two benchmarks in the 0.3V-1V supply voltage range. First, a NAND-NOR chain was considered. Simulation results showed that the DML approach assures roughly the 40% savings in terms of energy consumption with respect to the static CMOS implementation and improves the speed about 20% in comparison to the dynamic CMOS design. Second, a 16-bit Carry Skip Adder was considered. Due to the unique capability of the DML to switch on-the-fly between static and dynamic modes of operation, an improvement of more than 20% in terms of EDP was obtained in comparison to the conventional CMOS adder design.

The diminishing returns provided by voltage scaling have led to a recent paradigm shift toward so-called “approximate computing,” where computation accuracy is traded off for cost in error-tolerant applications. In this paper, a novel approach to achieving the power-performance-area versus data integrity tradeoff is proposed by integrating robust static memory cells and error-prone dynamic cells within a single array. In addition, the resulting integrated dynamic and static random access memory (iD-SRAM) provides the ability to trade off power consumption and accuracy on-the-fly according to the current conditions and operating mode. A 4-kB iD-SRAM array was implemented in a low-power, 65-nm CMOS technology, providing as much as an 80% power reduction and a 20% area reduction as compared with standard approaches, when applied to a video decoder at 500 MHz.

First-order and high-order correlation-power-analysis attacks have been shown to be a severe threat to cryptographic devices. As such, they serve as a security measure for evaluation and comparison of security-oriented implementations. When properly designed, data-dependent delays can be used as a barrier to these attacks. This paper introduces a security-oriented delay assignment algorithm for mitigating single and multibit attacks. The algorithm enables a reduction of the correlation between the processed data and the consumed current by utilizing the data-dependent delays as a source of correlated noise. This is done while minimizing the area overhead, propagation time, and power. We show that for the same security level this new algorithm provides X2 and X6 more area efficiency, and X1.5 and X2.25 higher frequencies than a permuted path delay assignment and random embedding of delay elements.

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configuration of the refresh rate according to the worst bitcell, when biased at low-probability, worst-case conditions. However, due to the process variations and local mismatch that can significantly deteriorate the data retention time of a GC-eDRAM bitcell, this design approach often leads to a large power overhead. In this paper, we present a novel GC-eDRAM architecture, incorporating several techniques for variation-aware operation. The primary feature of this architecture is an improved replica scheme for process compensated access tracking that enables calibration for process variations and adaptive refresh according to the array access statistics. The array is shown to ensure data integrity, providing as much as a 7x reduction in retention power over worst-case refresh-rate design for 20% write activity.

Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing control are explored considering as benchmarks basic logic gates as well as adders with different bit lengths. All the designed circuits were compared to their equivalent dynamic threshold voltage MOSFET (DTMOS) and conventional CMOS designs. The higher efficiency of low granularity body bias control is emphasized by the single well layout strategy, offered by the 28 nm UTBB FD-SOI technology, thus leading our approach to achieve competitive silicon area occupancy along with significant performance and energy improvements. More precisely, post-layout simulations have demonstrated that circuits designed according the suggested strategy, can achieve a delay reduction of 33% compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V. These results were obtained while maintaining robustness against process and temperature variations.

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32×32 bit memory macro was designed and fabricated in a standard 0.18-μm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.

Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18-μm CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

Side channel attacks have become one of the most significant problems in modern digital systems. In particular, differential power analysis (DPA) has emerged as a powerful technique because it does not require any assumptions regarding the hardware implementation of a crypto-chip. In this paper, a new randomized multitopology logic (RMTL) is proposed to enhance immunity to DPA. RMTL refers to a family of dedicated security-oriented gates whose power profile cannot be predicted by external observers. Specifically, each gate of this logic can be configured in real time to operate in a different circuit topology, where each topology induces a different power profile. Immunity to DPA attacks is obtained by randomly changing each gate's topology on run time. The suggested approach can coexist with common existing countermeasures. Theoretical analysis and simulation results, conducted in a standard 40-nm technology, clearly show higher immunity to DPA attacks when using the proposed approach compared with standard CMOS implementation.

Security of the digital systems is under the threat from so called side channel attacks. In particular, Differential Power Analysis (DPA) is a powerful technique, as it does not require any assumption regarding the chip implementation of the device. In this paper, we introduce a novel countermeasure strategy to deal with DPA attacks. This approach is based on randomization methodology of the Dual Mode Logic (DML) family. This logic family basically comprises two modes of operation: static and dynamic modes, each having a different power profile. We design the desired cryptographic module using DML gates while switching randomly between operation modes of these gates. This results in power profile which is much more difficult to estimate, and therefore makes the DPA attack less effective. Simulation results, conducted in a standard 40nm technology, prove the efficiency of the proposed methodology.

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.

A performance of the pseudo-random method for the radar detection is analyzed. The radar sends a pseudo-random sequence of length N, and receives echo from r targets. We assume the natural assumptions of uniformity on the channel and of the square root cancellation on the noise. Then for r ≤ N1-δ, where δ > 0, the following holds: (i) the probability of detection goes to one, and (ii) the expected number of false targets goes to zero, as N goes to infinity.

Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process.

This paper presents a hardware implementation of a digital watermarking system that can insert invisible, semifragile watermark information into compressed video streams in real time. The watermark embedding is processed in the discrete cosine transform domain. To achieve high performance, the proposed system architecture employs pipeline structure and uses parallelism. Hardware implementation using field programmable gate array has been done, and an experiment was carried out using a custom versatile breadboard for overall performance evaluation. Experimental results show that a hardware-based video authentication system using this watermarking technique features minimum video quality degradation and can withstand certain potential attacks, i.e., cover-up attacks, cropping, and segment removal on video sequences. Furthermore, the proposed hardware-based watermarking system features low power consumption, low cost implementation, high processing speed, and reliability.

A fundamental task in wireless communication is channel estimation: Compute the channel parameters a signal undergoes while traveling from a transmitter to a receiver. In the case of delay-Doppler channel, i.e., a signal undergoes only delay and Doppler shifts, a widely used method to compute the delay-Doppler parameters is the matched filter algorithm. It uses a pseudo-random sequence of length N, and, in case of non-trivial relative velocity between transmitter and receiver, its computational complexity is O(N2logN). In this paper we introduce a novel approach of designing sequences that allow faster channel estimation. Using group representation techniques we construct sequences, which enable us to introduce a new algorithm, called the flag method, that significantly improves the matched filter algorithm. The flag method finds m delay-Doppler parameters in O(mNlogN) operations. We discuss applications of the flag method to GPS, and radar systems.

In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept.

In this brief, an efficient voltage scalable switched capacitor converter (SCC) for 1.1 V battery-powered digital system is presented. The SCC employs a binary resolution technique to preserve high efficiency at load voltages down to sub-200 mV while keeping the efficiency high. The proposed converter can be configured into four topologies to support subthreshold output levels of 0.18-0.6 V. The converter is designed in a standard lowpower 40-nm CMOS TSMC process. Simulation results show that the efficiency of the SCC can be improved by 10%-11% in the vicinity of VDD=200 mV as compared to one using a conventional approach. An optimization strategy for designing multi-topology SCC is presented to improve the effectiveness of the circuit and to preserve efficiency over large load voltages.

A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low power low cost option for embedded RFID design. This cell requires the application of a 10V potential difference between the cell's control lines for program and erase operations. Providing the required voltages includes several challenges in the design of the voltage driver, such as the elimination of Gate Induced Drain Leakage (GIDL) currents. In this paper, we present a voltage driver architecture that utilizes novel techniques to overcome the power consumption problems during high voltage propagation. This driver was implemented in the TowerJazz 0.18μm CMOS technology, providing the required functionality with a low static-power figure of 34.6pW.

One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18µm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8µW during operation cycles.

A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.

A fundamental task in wireless communication is channel estimation: Compute the channel parameters a signal undergoes while traveling from a transmitter to a receiver. In the case of delay-Doppler channel, a widely used method is the matched filter algorithm. It uses a pseudo-random waveform of length N, and, in case of non-trivial relative velocity between transmitter and receiver, its computational complexity is O(N2log(N)). In this paper we introduce a novel approach of designing waveforms that allow faster channel estimation. Using group representation techniques we construct waveforms, which enable us to introduce a new algorithm, called the flag method, that significantly improves the matched filter algorithm. The flag method finds the channel parameters in O(m · N log(N)) operations, for channel of sparsity of order m. We discuss applications of the flag method to GPS, and radar system as well.

Near-threshold (NT) FFs, which operate from a supply voltage close to the transistor threshold voltage, are considered as a good alternative for portable applications, where low power dissipation with reasonable performance is the main demand. This paper presents an improved model for delay/energy estimation of the NT FFs. The proposed model, based on the EKV current and alpha power law models, improves the existing model by taking into account the rise and fall times of all internal nodes of the FF. The fitting parameters that are required for the model development were extracted from measurements of a test chip that was fabricated in a standard CMOS low power 80nm process. We show how the proposed model can be utilized for NT Master-Slave FF delay and energy estimation, showing an improvement of up to xlOO in the precision of calculations compared to the existing model.

In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing flip-flop cells, designed to operate in the subthreshold region. Both cells integrate a gate-diffusion input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the flip-flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90 nm process achieving a power dissipation of 8.4 nW in a typical corner at VDD = 300 mV with a delay of 51.7 nsec.

This paper presents a 128x128 low noise CMOS image sensor with emission filter for fluorescence detection. The imager, fabricated in 0.18 mum CMOS technology, provides low- noise operation by employing both the active reset (AR) technique and the active column sensor (ACS) readout method. The emission filter was fabricated using PDMS and Sudan II Blue dye mixed, spin-coated and deposited in the class 1000 clean room. The designed filter is suitable for excitation at wavelengths below 340 nm and emission at 450nm and above. Filter properties, such as thickness, transmission and efficiency of utilization with the fabricated imager are discussed. Preliminary measurements of the system using microbeads are also presented.

Fast development of low-power miniature CMOS sensors triggers their penetration to various applications, such as bio-medical applications, digital still and video cameras, cellular phones, web and security cameras and many other applications. The advantages of CMOS imagers over conventional CCD sensors are the possibility in integration of all functions required for timing, exposure control, color processing, image enhancement, image compression, analog-to-digital (ADC) conversion on the same chip and low-power operation. However, although CMOS imagers naturally provide low-power dissipation, their wide utilization in various portable battery-operated devices generates an increased demand for more aggressive power reduction. This paper presents a “smart” image sensor architecture and reviews general considerations for power reduction in CMOS image sensors at all possible design levels - technology, device, circuit, logic, architecture, algorithm and system integration.

An autonomous image sensor for real time target detection and tracking is presented. The sensor is based on a CMOS APS array, equipped with in-pixel functionality and integrates analog and digital components to achieve autonomous operation with minimal power dissipation. The system employs a two-phased operation flow; during the initial acquisition stage, the digital controller detects and acquires the brightest targets in the field of view within a single frame and defines windows of interest (WOI) around the center of mass coordinates of each object. Subsequently, the system moves into the analog tracking mode during which all areas outside of the WOI are entirely shut down, thus saving power to a number of orders of magnitude. In addition to its low power dissipation, the sensor features real-time operation, low fixed pattern noise, linearity and the ability to track a predefined number of targets throughout the entire field of view. A 64x64 pixel sensor array has been designed in 0.18μm CMOS technology and is operated via a 1.8V supply. The imager architecture is discussed, the circuits’ descriptions are shown and simulation results are presented.

A low power CMOS image sensor employing Adaptive Bulk Biasing Control (AB2C) approach is presented. The AB2C is a novel method that utilizes self adaptive biasing of the sensor array and digital periphery and allows sensor power reduction and image performance improvement. The presented AB2C technique can be easily implemented in a standard twin well or triple well CMOS technology. Both rolling shutter and global shutter imagers were examined using the AB2C, showing increased sensor output voltage swing, reduced in-pixel leakage currents, increased shutter efficiency and significant improvement in power dissipation of the scanning circuitry. A detailed description and analysis of the AB2C method is presented. Various image sensors employing AB2C have been implemented in a standard 0.18μm CMOS technology available through MOSIS and are operated via a 1.8V supply. Imagers operation is discussed and simulation results are reported.

Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.