Nectar is a high-speed fiber-optic network developed as a network backplane to support distributed and heterogeneous computing. A distinguishing component of the Nectar network is a highly programmable network processor called the communication accelerator board (CAB). The Nectar CAB has a flexible architecture, where almost all interactions between the network and the host are programmable. This structure allows arbitrary protocols to be implemented, evaluated, and utilized. A description is presented of the design, implementation, and usage of the Nectar CAB, and performance implications of its hardware features are discussed.>

ATM (asynchronous transfer mode) is an international telecommunications standard designed for broadband integrated services; it is also well-suited for use within local-area networks. ATM LANs can provide the networking support needed for multimedia communication at rates of 100 Mbits/sec and higher. The authors first analyze the protocol processing required to handle ATM communication. Based on this analysis, they then discuss the architectural issues in the design of host interfaces for ATM local-area networks. In particular, they conclude that a simple host interface, which leaves most of the ATM protocol processing to be done by the host computer, supports good performance for data communication (around 100 Mbits/sec). However, to support real-time video and audio communication, the ATM interface should include an embedded processor.>

Multicomputersbuiltaround a general network are now a viable alternative to multicomputersbased on a system-speci~c interconnect because of architectural improvements in two areas.First, the host-network interface overhead can be minimized by reducing copy operations and host interrupts.Second, the network can provide high bandwidth and low latency by using high-speed crossbar switches and efficient protocol implementations.While still enjoying thejexibility of general networks, the resulting network-based multicomputers achieve high performance for typical multicomputer applications that use system-specijic interconnects.We have developed a network-based mtdticomputer called Nectar that supports these claims.

The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increased computational bandwidth. Warp is integrated as an attached processor into a Unix host system. Programs for Warp are written in a high-level language supported by an optimizing compiler. The first ten-cell prototype was completed in February 1986; delivery of production machines started in April 1987. Extensive experimentation with both the prototype and production machines has demonstrated that the Warp architecture is effective in the application domain of robot navigation as well as in other fields such as signal processing, scientific computation, and computer vision research. For these applications, Warp is typically several hundred times faster than a VAX 11/780 class computer. This paper describes the architecture, implementation, and performance of the Warp machine. Each major architectural decision is discussed and evaluated with system, software, and application considerations. The programming model and tools developed for the machine are also described. The paper concludes with performance data for a large number of applications.

Warp is a programmable systolic array machine designed by CMU and built together with its industrial partners-GE and Honeywell. The first large scale version of the machine with an array of 10 linearly connected cells will become operational in January 1986. Each cell in the array is capable of performing 10 million 32-bit floating-point operations per second (10 MFLOPS). The 10-cell array can achieve a performance of 50 to 100 MFLOPS for a large variety of signal processing operations such as digital filtering, image compression, and spectral decomposition. The machine, augmented by a Boundary Processor, is particularly effective for computationally expensive matrix algorithms such as solution of linear systems, QR-decomposition and singular value decomposition, that are crucial to many real-time signal processing tasks. This paper outlines the Warp implementation of the 2- dimensional Discrete Cosine Transform and singular value decomposition.

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

A high-performance systolic array computer has been designed by CMU and is currently under construction. The first copy of the machine, to be built by CMU together with its industrial partners before the end of 1985, will incorporate a programmable systolic array of ten linearly connected cells. Each cell in the systolic array is capable of performing 10 million floating-point operations per second (10 MFLOPS), giving the total machine a peak performance of 100 MFLOPS, or higher if additional cells are used. This particular systolic array computer is named Warp, suggesting that it can perform computations at a very high speed. The 10-cell systolic array, with one cell implemented on one board, can process 1024-point complex FFTs at a rate of one FFT every 600 µs. Under program control, the same array can perform many other primitive computations in signal, image, and vision processing, including two-dimensional convolution, dynamic programming, and real or complex matrix multiplication, at a rate of 100 million floating-point operations per second. Users may view the systolic array as an array of conventional "array processors," which can efficiently implement not only systolic algorithms where communication between adjacent cells is intensive, but also non-systolic algorithms where each cell operates on its own data independently from the rest. This paper describes the hardware organization of the Warp machine.