EDBT 2026 Demo / reviewers in the wild / expert
Theodore M. Wong
dblp:97/6834
· DBLP profile ↗
7ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-authorArtificial intelligence and machine learning · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Storage systems · 26% Emerging computing paradigms · 19% Performance modeling and evaluation · 19% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms
neuromorphic computing |
0.1 | 1 | 2012 | Compass: a scalable simulator for an architecture for cognitive computing · SC 2012 |
Performance modeling and evaluation
simulation |
0.1 | 1 | 2012 | Compass: a scalable simulator for an architecture for cognitive computing · SC 2012 |
Storage systems › i/o scheduling
disk scheduling |
0.1 | 1 | 2008 | Efficient guaranteed disk request scheduling with fahrrad · EuroSys 2008 |
Storage systems
i/o scheduling |
0.1 | 1 | 2008 | Efficient guaranteed disk request scheduling with fahrrad · EuroSys 2008 |
Embedded and real-time systems
real-time scheduling |
0.1 | 1 | 2008 | Efficient guaranteed disk request scheduling with fahrrad · EuroSys 2008 |
High-performance computing › supercomputer architecture
blue gene/q |
0.0 | 1 | 2012 | Compass: a scalable simulator for an architecture for cognitive computing · SC 2012 |
High-performance computing › large-scale simulation
massively parallel simulation |
0.0 | 1 | 2012 | Compass: a scalable simulator for an architecture for cognitive computing · SC 2012 |
Memory systems
cache |
0.0 | 1 | 2002 | My Cache or Yours? Making Storage More Exclusive · USENIX ATC, General Track 2002 |
Memory systems › cache management
cache replacement |
0.0 | 1 | 2002 | My Cache or Yours? Making Storage More Exclusive · USENIX ATC, General Track 2002 |
Memory systems › memory hierarchy › cache hierarchy management
exclusive caching |
0.0 | 1 | 2002 | My Cache or Yours? Making Storage More Exclusive · USENIX ATC, General Track 2002 |
Storage systems
storage hierarchy |
0.0 | 1 | 2002 | My Cache or Yours? Making Storage More Exclusive · USENIX ATC, General Track 2002 |
Methods — techniques the papers use, named apart from their topics
parallel compiler · 0.1multithreaded simulation · 0.1PGAS communication · 0.1utilization-based reservation · 0.1schedulability proof · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic coresabstractMarching along the DARPA SyNAPSE roadmap, IBM unveils a trilogy of innovations towards the TrueNorth cognitive computing system inspired by the brain's function and efficiency. The sequential programming paradigm of the von Neumann architecture is wholly unsuited for TrueNorth. Therefore, as our main contribution, we develop a new programming paradigm that permits construction of complex cognitive algorithms and applications while being efficient for TrueNorth and effective for programmer productivity. The programming paradigm consists of (a) an abstraction for a TrueNorth program, named Corelet, for representing a network of neurosynaptic cores that encapsulates all details except external inputs and outputs; (b) an object-oriented Corelet Language for creating, composing, and decomposing corelets; (c) a Corelet Library that acts as an ever-growing repository of reusable corelets from which programmers compose new corelets; and (d) an end-to-end Corelet Laboratory that is a programming environment which integrates with the TrueNorth architectural simulator, Compass, to support all aspects of the programming cycle from design, through development, debugging, and up to deployment. The new paradigm seamlessly scales from a handful of synapses and neurons to networks of neurosynaptic cores of progressively increasing size and complexity. The utility of the new programming paradigm is underscored by the fact that we have designed and implemented more than 100 algorithms as corelets for TrueNorth in a very short time span. Arnon Amir, Pallab Datta, William P. Risk, Andrew S. Cassidy, Jeffrey A. Kusnitz, Steven K. Esser, Alexander Andreopoulos, Theodore M. Wong, Myron Flickner, Rodrigo Alvarez-Icaza, Emmett McQuinn, Ben Shaw 0001, Norm Pass, Dharmendra S. Modha |
IJCNN | 8 |
| 2013 | Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic coresabstractMarching along the DARPA SyNAPSE roadmap, IBM unveils a trilogy of innovations towards the TrueNorth cognitive computing system inspired by the brain's function and efficiency. Judiciously balancing the dual objectives of functional capability and implementation/operational cost, we develop a simple, digital, reconfigurable, versatile spiking neuron model that supports one-to-one equivalence between hardware and simulation and is implementable using only 1272 ASIC gates. Starting with the classic leaky integrate-and-fire neuron, we add: (a) configurable and reproducible stochasticity to the input, the state, and the output; (b) four leak modes that bias the internal state dynamics; (c) deterministic and stochastic thresholds; and (d) six reset modes for rich finite-state behavior. The model supports a wide variety of computational functions and neural codes. We capture 50+ neuron behaviors in a library for hierarchical composition of complex computations and behaviors. Although designed with cognitive algorithms and applications in mind, serendipitously, the neuron model can qualitatively replicate the 20 biologically-relevant behaviors of a dynamical neuron model. Andrew S. Cassidy, Paul Merolla, John V. Arthur, Steven K. Esser, Bryan L. Jackson, Rodrigo Alvarez-Icaza, Pallab Datta, Jun Sawada, Theodore M. Wong, Vitaly Feldman, Arnon Amir, Daniel Ben Dayan Rubin, Filipp Akopyan, Emmett McQuinn, William P. Risk, Dharmendra S. Modha |
IJCNN | 9 |
| 2013 | Cognitive computing systems: Algorithms and applications for networks of neurosynaptic coresabstractMarching along the DARPA SyNAPSE roadmap, IBM unveils a trilogy of innovations towards the TrueNorth cognitive computing system inspired by the brain's function and efficiency. The non-von Neumann nature of the TrueNorth architecture necessitates a novel approach to efficient system design. To this end, we have developed a set of abstractions, algorithms, and applications that are natively efficient for TrueNorth. First, we developed repeatedly-used abstractions that span neural codes (such as binary, rate, population, and time-to-spike), long-range connectivity, and short-range connectivity. Second, we implemented ten algorithms that include convolution networks, spectral content estimators, liquid state machines, restricted Boltzmann machines, hidden Markov models, looming detection, temporal pattern matching, and various classifiers. Third, we demonstrate seven applications that include speaker recognition, music composer recognition, digit recognition, sequence prediction, collision avoidance, optical flow, and eye detection. Our results showcase the parallelism, versatility, rich connectivity, spatio-temporality, and multi-modality of the TrueNorth architecture as well as compositionality of the corelet programming paradigm and the flexibility of the underlying neuron model. Steven K. Esser, Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Davis Barch, Arnon Amir, John V. Arthur, Andrew S. Cassidy, Myron Flickner, Paul Merolla, Shyamal Chandra, Nicola Basilico, Stefano Carpin, Thomas G. Zimmerman, Frank Zee, Rodrigo Alvarez-Icaza, Jeffrey A. Kusnitz, Theodore M. Wong, William P. Risk, Emmett McQuinn, Tapan K. Nayak, Raghavendra Singh, Dharmendra S. Modha |
IJCNN | 18 |
| 2012 | Compass: a scalable simulator for an architecture for cognitive computingabstractInspired by the function, power, and volume of the organic brain, we are developing TrueNorth, a novel modular, non-von Neumann, ultra-low power, compact architecture. TrueNorth consists of a scalable network of neurosynaptic cores, with each core containing neurons, dendrites, synapses, and axons. To set sail for TrueNorth, we developed Compass, a multi-threaded, massively parallel functional simulator and a parallel compiler that maps a network of long-distance pathways in the macaque monkey brain to TrueNorth. We demonstrate near-perfect weak scaling on a 16 rack IBM® Blue Gene®/Q (262144 CPUs, 256 TB memory), achieving an unprecedented scale of 256 million neurosynaptic cores containing 65 billion neurons and 16 trillion synapses running only 388x slower than real time with an average spiking rate of 8.1 Hz. By using emerging PGAS communication primitives, we also demonstrate 2x better real-time performance over MPI primitives on a 4 rack Blue Gene/P (16384 CPUs, 16 TB memory). Robert Preissl, Theodore M. Wong, Pallab Datta, Myron Flickner, Raghavendra Singh, Steven K. Esser, William P. Risk, Horst D. Simon, Dharmendra S. Modha |
SC | 2 |
| 2008 | Efficient guaranteed disk request scheduling with fahrradabstractGuaranteed I/O performance is needed for a variety of applications ranging from real-time data collection to desktop multimedia to large-scale scientific simulations. Reservations on throughput, the standard measure of disk performance, fail to effectively manage disk performance due to the orders of magnitude difference between best-, average-, and worst-case response times, allowing reservation of less than 0.01 % of the achievable bandwidth. We show that by reserving disk resources in terms of utilization it is possible to create a disk scheduler that supports reservation of nearly 100 % of the disk resources, provides arbitrarily hard or soft guarantees depending upon application needs, and yields efficiency as good or better than best-effort disk schedulers tuned for performance. We present the architecture of our scheduler, prove the correctness of its algorithms, and provide results demonstrating its effectiveness. Anna Povzner, Tim Kaldewey, Scott A. Brandt, Richard A. Golding, Theodore M. Wong, Carlos Maltzahn |
EuroSys | 5 |
| 2008 | Virtualizing Disk PerformanceabstractLarge- and small-scale storage systems frequently serve a mixture of workloads, an increasing number of which require some form of performance guarantee. Providing guaranteed disk performance - the equivalent of a "virtual disk" - is challenging because disk requests are non-preemptible and their execution times are stateful, partially non-deterministic, and can vary by orders of magnitude. Guaranteeing throughput, the standard measure of disk performance, requires worst-case I/O time assumptions orders of magnitude greater than average I/O times, with correspondingly low performance and poor control of the resource allocation. We show that disk time utilization- analogous to CPU utilization in CPU scheduling and the only fully provisionable aspect of disk performance - yields greater control, more efficient use of disk resources, and better isolation between request streams than bandwidth or I/O rate when used as the basis for disk reservation and scheduling. Tim Kaldewey, Theodore M. Wong, Richard A. Golding, Anna Povzner, Scott A. Brandt, Carlos Maltzahn |
IEEE Real-Time and Embedded Technology and Applications Symposium | 2 |
| 2002 | My Cache or Yours? Making Storage More Exclusive
Theodore M. Wong, John Wilkes |
USENIX ATC, General Track | 1 |