Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, the authors propose a heterogeneous power model to estimate the power utilized by complete processor based reconfigurable system-on-chip (SoC) platform. The proposed model estimates the power consumed by the SoC platform using instruction-based model as well as transaction-based model. In addition the authors estimate the power consumed by various bus arbitration policies used in the on-chip communication