This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown.

Selective change-driven (SCD) vision is a capture/processing strategy especially suited for vision systems with limited resources and/or vision applications with real-time constraints. SCD vision capture essentially involves delivering only the pixels that have undergone the greatest change in illumination since the last time they were read-out. SCD vision processing involves processing a limited pixel flow with similar results to the usual image flow, but with far lower bandwidth and processing requirements. SCD vision is based on pixel flow processing instead of traditional image flow processing. This complete change in the way video is processed and has a direct impact on the processing hardware required to deal with visual information. In this paper, we present the first CMOS sensor using the SCD strategy, along with a highly resource-limited system implementing an object tracking experiment. Results show that SCD vision outperforms traditional vision systems by at least one order of magnitude, with limited hardware requirements for the specific tracking experiment being tested.

Modelling of physical phenomena often involves the use of complex systems of equations whose computational solution has demanding requirements in terms of memory and computing power. Among the different techniques proposed, the Finite-Difference Time-Domain (FD-TD) method has the advantage of a feasible hardware implementation that can significantly speed up the computations. This technique is widely used for the solution of partial differential equations in a variety of areas such as antennas design, medical studies, circuit packaging and non-destructive evaluation. In this paper, we present a hardware accelerator of a 3D FD-TD heat equation solver that constitutes the basis of a thermal model of the soil for the non-destructive evaluation of minefields using infrared thermography techniques. In order to be able to work on the field during mine removal activities, a portable and computationally efficient system must be achieved. To this aim, we projected the 3D FD-TD model of the soil onto an FPGA platform using Handel-C and VHDL. A speedup factor of 34 over a single precision PC (C++) is achieved.

Modeling of physical phenomena often involves the use of complex sets of equations whose computational solution has demanding requirements in terms of memory and computing power. Finite-Difference Time-Domain (FD-TD) method is a technique widely used nowadays in a variety of areas, such as antennas design, medical studies, circuit packaging and non destructive evaluation (NDE), having the advantage of a feasible hardware implementation of the algorithm that can significantly speedup the computations. In this paper we will focus on the thermal modeling of the soil for NDE. To this aim we projected a true 3D FD-TD model of the soil on an FPGA. Two different implementations of the system were made, one developed with VHDL and another one with Handel-C. A speed-up factor of 160 over a PC is achieved which shows the utility of such an implementation.

Infrared thermography is a technique for the detection of plastic mines. Its application requires the solution of the equations that govern the heat transfer processes. We present an FPGA projection of a system that solves these equations

Optical flow computation has been extensively used for object motion estimation in image sequences. However, the results obtained by most optical flow techniques are as accurate as computationally intensive due to the large amount of data involved. A new strategy for image sequence processing has been developed; pixels of the image sequence that significantly change fire the execution of the operations related to the image processing algorithm. The data reduction achieved with this strategy allows a significant optical flow computation speed up. Furthermore, FPGAs allow the implementation of a custom data-flow architecture specially suited for this strategy. The bases of the change-driven image processing are presented, as well as the hardware custom implementation

The use of infrared (IR) images of the soil is an efficient technique to detect shallowly buried landmines. The detection is possible due to the different thermal properties of the soil and the mine. The core of this technique is the simulation of the heat transfer processes in the soil and at the soil-air interface. Simulation of these processes is a very long-time consuming task on ordinary computers. Its execution on dedicated hardware can reduce the computing time. In this paper we show the architecture of a system that simulates the thermal processes onto an FPGA, showing the feasibility of such a realization.