Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of the CAESAR authenticated encryption competition. In this paper, the promising CAESAR candidate ASCON is implemented in hardware and optimized for different typical applications to fully explore ASCON's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an ASCON implementation with a single unrolled round transformation is only 7 kGE large, but can process up to 5.5 Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, ASCON is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of ASCON just requires about 8 kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.

Identity-based encryption constitutes a promising alternative to traditional cryptography that works without symmetric keys or public key infrastructures. Such schemes generally depend on the computation of bilinear pairings. The latest developments in efficient pairing algorithms made identity-based encryption available to embedded devices as well. However, those devices are inherently exposed to side-channel attacks. In this paper, we present a correlation power analysis attack to extract the private key in the popular identity-based encryption scheme by Boneh and Boyen. On an ARM Cortex-M0 we exploit the leakage of a finite field multiplication within the highly practical optimal-Ate pairing defined over the elliptic curves by Barreto and Naehrig. As a secondary contribution, we practically verified the feasibility of our attack on an FPGA, an ASIC, and using power simulations. For future work our research intends to raise awareness of the importance of the randomization countermeasure in pairing computations.

JAAVR stands for Just Another AVR, is a clone of the popular ATmega128 microprocessor, and is used as the core component of a security-enabled RFID tag. First, we evaluate different hardware designs using JAAVR to communicate via ISO 14443A. Second, we implement AES, Gr{\o}stl and Elliptic Curve Cryptography (ECC) and present several new runtime and low-memory records. Third, we add those assembly-optimized implementations to our RFID platform and investigate their impact in chip area and power consumption. Our designs are fully synthesizable as ASIC and FPGA and were tested using a discrete analog front-end and a standard RFID reader.