In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit's behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented.>

In this paper a new approach, called BETA, for computing testability is presented. The approach is based on analyzing the circuit's behavioral description: the control flow graph (CFG). Based on path analysis, testability measures are derived. Unlike a traditional testability measure which computes testability, our approach also derives the exact sequence for justifying and propagating the contents of each variable when possible. Variable classification is used to diagnose every register's controllability and observability and to classify them into several groups. Based upon this classification, guidance is provided to the test generator for each group. Variable classification is also useful in pointing out hard-to-control and hard-to-observe areas of a circuit. For fully controllable and observable variables, the best path sequence to justify and propagate these registers is generated. This approach has been implemented in a computer program and applied to several examples. All these results are verified by a CFG-based test generator and proven to be successful.>

A synthesis for testability approach is presented. In this approach test points or flip-flops to be used in test point insertion or partial scan to enhance circuit testability are selected. The selection is based on circuit behavioral information rather than low level structural description. This allows test point insertion or partial scan usage on circuits described as interconnections of high level modules. Test statement insertion is also proposed as an alternative to test point insertion and to partial scan. The major advantage of using test statement insertion is a lower pin count and lower test application time overhead than test point insertion and partial scan. The tool has been implemented in a computer program.>

An approach, Beta, for computing testability is presented. This approach is based on analyzing the circuit's behavior description data flow graph (DFG). First, each path in the DFG is analyzed to find the set of paths to justify and propagate each data register. Then, register classification follows to diagnose every register's controllability and observability and classify them into several groups. For the most controllable and observable registers, Beta, unlike other testability methods which compute only testability, also tries to derive the exact sequence for justifying and propagating each register. Register classification is also useful in pointing out hard-to-control and hard-to-observe areas of the circuit. This approach has been implemented in a computer program and applied to several examples. These results are verified by a DFG-based test generator and proven to be successful.>

Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nodes are accessible. A simple modification to the DFG that increases accessibility is presented.>