We propose a fully asynchronous peak detection approach for SPAD-based direct Time-of-Flight (dToF) flash LiDAR, enabling pixel-wise event-driven depth acquisition without global synchronization. By allowing pixels to independently report depth once a sufficient signal-to-noise ratio is achieved, the method reduces latency, mitigates motion blur, and increases effective data rate compared to frame-based systems. The framework is validated under two hardware implementations: an offline$256\times 128$SPAD array with PC based processing and a real-time FPGA proof-of-concept prototype with$2.4\mu $s latency for on-chip integration. Experiments demonstrate robust depth estimation, reflectivity reconstruction, and dynamic event-based representation under both static and dynamic conditions. The results confirm that asynchronous operation reduces redundant background data and computational load, while remaining tunable via simple hyperparameters. These findings establish a foundation for compact, low-latency, event-driven LiDAR architectures suited to robotics, autonomous driving, and consumer applications. In addition, we have derived a semi-closed-form solution for the detection probability of the raw-peak finding based LiDAR systems that could benefit both conventional frame-based and proposed asynchronous LiDAR systems.

In this paper, we present a novel asynchronous peak detection method for Direct Time-of-Flight (dToF) flash LiDAR systems. The approach allows to adjust the exposure time in each pixel based on thresholding the maximum of the histogram with a statistical confidence level. By asynchronously reporting peak events instead of entire frames, our approach significantly reduces latency and enhances photon efficiency. Implemented on a Xilinx Kintex-7 FPGA and tested on a 128x64 SPAD array, the method demonstrates improved motion blur mitigation. This technique holds promise for applications such as autonomous vehicles and augmented reality, where rapid and accurate depth sensing is essential.

Single-photon Light Detection and Ranging (LiDAR) systems are often equipped with an array of detectors for improved spatial resolution and sensing speed. However, given a fixed amount of flux produced by the laser transmitter across the scene, the per-pixel Signal-to-Noise Ratio (SNR) will decrease when more pixels are packed in a unit space. This presents a fundamental trade-off between the spatial resolution of the sensor array and the SNR received at each pixel. Theoretical characterization of this fundamental limit is explored. By deriving the photon arrival statistics and introducing a series of new approximation techniques, the Mean Squared Error (MSE) of the maximum-likelihood estimator of the time delay is derived. The theoretical predictions align well with simulations and real data.

This paper studies complex modulation schemes, including orthogonal frequency-division multiplexing (OFDM), received by a single photon avalanche diode (SPAD) array integrated circuit (IC). A SPAD operates in the Geiger mode, and is able to detect single photons. This feature enables order of magnitude receiver sensitivity in intensity modulation (IM) / direct detection (DD) Visible Light Communication (VLC) systems. The tradeoff between received power and bit error ratio (BER) using both pulse-amplitude modulation (PAM) and OFDM is shown. A first order model of the noise in a digital SPAD receiver is derived. The noise in the experimental receiver chip approaches the predicted noise in our model, and we achieve receiver sensitivity of $-$64 dBm with a 100 kbit/s signal at a BER of 10^-5. It is concluded that future improvements in SPAD VLC receiver architecture will allow sensitivity to approach the quantum limit.

In this paper an energy efficient light emitting diode (LED) driver circuit for visible light communications (VLC) and results from the electrical and optical characterization are presented. A current steering digital to analogue converter (DAC) based LED driver circuit supporting 4-channels with an 8-bit resolution is realized in a 0.18 μm complimentary metal oxide semiconductor (CMOS) technology. Each channel delivers a full-scale current of 255 mA and achieves up to 67% electrical efficiency when driving 250 MS/s orthogonal frequency division multiplexing (OFDM) signals. Optical differential drive capability is demonstrated by using two output branches of a single channel to drive two different LEDs with an SNR improvement (>5 dB). The chip is also capable of full digital control of color shift keying (CSK) using multi-color LEDs enabling lighting color-temperature adjustment, dimming and multiple-input and multiple-output (MIMO) optical communications and these aspects will be the subject of future research.

Visible light communications (VLC) has the potential to play a major part in future smart home and next generation communication networks. There is significant ongoing work to increase the achievable data rates using VLC, to standardize it and integrate it within existing network infrastructures. The future of VLC systems depends on the ability to fabricate low cost transceiver components and to realize the promise of high data rates. This paper reports the design and fabrication of integrated transmitter and receiver components. The transmitter uses a two dimensional individually addressable array of micro light emitting diodes (μLEDs) and the receiver uses an integrated photodiode array fabricated in a CMOS technology. A preliminary result of a MIMO system implementation operating at a data rate of 1 Gbps is demonstrated. This paper also highlights the challenges in achieving highly parallel data communication along with the possible bottlenecks in integrated approaches.

Poisson distributed spike trains are often used as the input to VLSI implementations of spiking neural networks. However, it can be difficult to generate large truly random spike distributions which can be easily applied as input to a chip. This work presents results recorded from an avalanche photo diode which demonstrates that it can be used to create a Poisson distributed spike train and describes the circuitry which will allow it to interface with other neuromorphic chips using the Address Event Representation protocol. The chip is currently being fabricated using the AMS 0.35μm HV process.

A 1 GHz 7-bits flash A/D converter is fabricated in 90 nm CMOS technology to be used as part of an analog front end (AFE) for digitising of OFDM communication signals. To extend the receiver bandwidth, input capacitance-reducing techniques are used. The motivation in implementing a non-uniform resolution step and the challenges in its physical implementation are discussed. To further reduce the input capacitance, small geometries are used in the comparator input pair, where the offset is corrected by a number of calibration strategies. The converter achieves extended resolution and SNR, and input bandwidth compared to conventional architectures.

A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32times32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.

An NMOS only class-D output driver which uses charge pump techniques in a low voltage CMOS technology is presented. Compared to conventional class-D output stages, the given implementation shows a gate area reduction of 45%, resulting in efficiency improvements. The circuit has been simulated in a 0.13 mum process and is implemented using 3.3 V I/O devices. The structure does not violate any gate-oxide reliability rules.

The use of oversampling to reduce I/O requirements of time-to-digital converters for arrays of high precision photonic detectors is considered. Simulation results show that the high linearity offered by oversampled converters can be applied to time estimation. The averaging and lowpass filtering inherent in these techniques reduce jitter and enhance estimates of mean time delay. Various sigma-delta TDC architectures are studied in the presence of background illumination noise with reference to time-of-flight Ladar and time-correlated fluorescence detection applications