FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a fully invertible FPGA architecture. In this architecture, two small modules are introduced to make the bitstream of logic and routing resources of the FPGA tiles fully invertible. Accordingly, to insert recovery cycles in the lifetime of the transistors, the bitstream stored in the configuration SRAM cells can be inverted occasionally without any changes in the functionality of the design. Using the proposed architecture, it is neither required to repeat the placement and routing procedures to generate multiple configuration bitstreams, nor extra memory is needed to save alternative bitstreams for changing the SRAM cells contents. Our experimental results over a set of industrial benchmarks show that by choosing an appropriate switch block arrangement and an optimized flipping frequency, the proposed architecture can improve the aging induced performance degradation by up to 62.5% with acceptable power and area overheads on logic and routing resources.

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.