Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

Quantum-dot cellular automata (QCA) is attracting a lot of attention due to its extremely small feature size and ultralow power consumption. Up to now, several adder designs using QCA technology have been proposed. However, it was found that not all of the designs function properly. This paper analyzes the reasons of the failures and proposes adders that exploit proper clocking schemes

Task preemption is a critical enabling mechanism in multitask very large scale integration (VLSI) systems. On preemption, data in the register files must be preserved for the task to be resumed. This entails extra memory to preserve the context and additional clock cycles to save and restore the context. In this paper, techniques and algorithms to incorporate micropreemption constraints during multitask VLSI system synthesis are presented. Specifically, algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints, techniques to minimize the context switch overhead by considering the dedicated registers required to save the state of a task on preemption and the shared registers required to save the remaining values in the tasks, and a controller-based scheme to preclude the preemption-related performance degradation by: 1) partitioning the states of a task into critical sections; 2) executing the critical sections atomically; and 3) preserving atomicity by rolling forward to the end of the critical sections on preemption have been developed. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on real examples. Validation of all the results is complete in the sense that functional simulation is conducted to complete layout implementation.

Quantum-dot cellular automata (QCA) are attracting a lot of attention due to their extremely small feature sizes and ultra low power consumption. Several designs using QCA technology have been proposed. However, we have found that not all of the designs function properly. Further, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing large scale circuits using QCA technology an extremely time-consuming process. We show several critical vulnerabilities in the structures of primitive QCA gates and QCA interconnects, and propose a disciplinary guideline to prevent any additional plausible, but malfunctioning, QCA designs.

Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded lC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis: Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

Synthesis of Application Specific ProgrammableProcessors poses numerous new tasks onbehavioral synthesis tools.We address some ofthem including application bundling.ApplicationBundling is a synthesis task where n control-data flowgraphs are bundled into at most m groups, so that eachapplication belongs to at least one group and throughputconstraints for all applications are satisfied.We have shown how a variety of application specificconstraints such as manufacturing cost reduction andproduction risk reduction can be targeted during thesynthesis process.The effectiveness of our approach isdemonstrated on a number of real examples.

Numerous fast algorithms for the DiscreteCosine Transform (DCT) have been proposed. Until recently, it has been difficult to compare different DCT algorithms and select one which is best suitedfor implementation under a given set of design goals.We propose an approach for design space explorationat the algorithm and behavioral levels using behavioral synthesis tools and demonstrate its effectiveness for designing DCT ASIC. In particular, we study andcompare the following nine DCT algorithms: Lee's,Wang's, DIT, DFT, Arai's, DIF, Vetterli's, planar rotation, and direct algorithm. The main conclusions of this study are (i) the best choice among fast DCT algorithms depends on a particular set of design goals and constraints and (ii) almost always more than anorder of magnitude improvement can be achieved using algorithm and behavioral design space exploration.

Task preemption is a critical enabling mechanism in multi-task VLSI systems. On preemption, data in the register files must be preserved in order for the task to be resumed. This entails extra memory to save the context and additional clock cycles to restore the context. We present techniques and algorithms to incorporate micro-preemption constraints during multi-task VLSI system synthesis. Specifically, we have developed: algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints; techniques to minimize the context switch overhead by considering the dedicated registers required to save the state of a task on preemption and the shared registers required to save the remaining values in the tasks; and a controller based scheme to preclude preemption related performance degradation.

Using the flexibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous Built-In-Resiliency (HBIR). HBIR processor synthesis imposes several unique tasks on the synthesis process: (i) latency determination targeting k-unit fault-tolerance, (ii) application-to-faulty-unit matching and (iii) HBIR scheduling and assignment algorithms. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of designs.