This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to 26× and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

This presentation discusses on the comparison between "Reconfigurable Chip with High Level Synthesis" and "CPU, GPCPU with compiler such as CUDA" from the compiler perspective. Initially, we introduce several demands for acceleration with FPGA to achieve low latency calculation and control. As an application example, we show a High Frequency Trading. We accelerate it by FPGA NIC with C-based and SQL-based HLS, and show the necessity of high level language customizable reconfigurable chip. Then, we illustrate the difference of FPGA and processor (CPU, GPGPU) with the "FSM+Datapath" model and examine how the architecture difference affects delay and parallelism of operations. Next, we discuss parallelization of operations, threads with High Level Synthesis for FPGA and software compiler for processors. The main advantage of the former method is it is able to parallelize operations beyond control dependencies while the latter method has to obey control dependencies. Finally, some experimental results prove that "FPGA and HLS" generate better performance than a processor for control intensive algorithm.

This presentation discusses how FPGA or coarse grained reconfigurable processor is superior to CPU/GPGPU from the view point of C compiler. Initially, we introduce the architectural characteristic of CPU, GPGPU and fine grained and coarse grained reconfigurable process with FSM+Datapath model. Then, we explain what kind of applications can be accelerated with "FPGA and C-based High Level Synthesis Tool" better than GPGPU according to the compiler techniques (freedom of compiler parallelization).

A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for high-level synthesis based on a divide and conquer method called Divide and Conquer Exploration Algorithm (DC-ExpA) is presented. DC-ExpA parses an untimed behavioral description given in C or SystemC and clusters interdependent operations which are in turn explored independently by inserting synthesis directives automatically in the source code. The method then continues by combining the exploration results to obtain only Pareto-optimal designs. This method accelerates the design space exploration considerably and is compared against two previous methods: an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) that shows good optimality at high runtimes, and a pattern matching method called Clustering Design Space Exploration Acceleration (CDS-ExpA) that is fast but suboptimal. Our proposed method is orthogonal to previous exploration methods that focus on the exploration of resource constraints, allocation, binding, and/or scheduling. Our proposed method on contrary sets local synthesis directives that decide upon the overall architectural structure of the design (e.g., mapping certain arrays to memories or registers). Results show that DC-ExpA explores the design space on average 61% faster than ASA-ExpA, obtaining comparable results indicated by several quality indicators, for example, distance to reference Pareto-front, hypervolume, and Pareto dominance. Compared to CDS-ExpA it is 69% slower, but obtains much betters results compared to the same quality indicators.

This work presents the design of a complex image processing IP developed completely in C. We present the latest advanced in ESL-synthesis and demonstrate its main advantages over conventional RT-level flows. In particular we focus on the ability of behavioral synthesis to shorten the design cycle, perform functional verification and explore quickly the design space obtaining multiple dominating implementations with unique area vs. speed characteristics from an initial untimed behavioral description. A feature extraction process is presented in detailed showing how automatic design space exploration can lead to Pareto optimal (non-dominant) designs ranging from 524,648 gates to 584,868 gates and latencies of 38 to 69 state counts for the smallest and fastest design respectively taking approximately 6.3 hours.

This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-consuming differential equations to obtain the hotspots, we propose a fast and accurate heuristic model based on power budgeting to plan the dynamic placements of the design statically, while considering the boundary conditions. Based on our heuristic model, we have developed a fast optimization technique to plan the dynamic placements at design time. Our results indicate that our technique is two orders of magnitude faster while the quality of the placements generated in terms of temperature and interconnection overhead is the same, if not better, compared to the thermal-aware placement techniques which perform thermal simulations inside the search engine.

This paper presents a clustering method called clustering design space exploration (CDS-ExpA) to accelerate the architectural exploration of behavioral descriptions in C and SystemC. The trade-offs between faster exploration versus optimality of results are investigated. Two variations of CDS-ExpA were developed: CDS-ExpA(min) and CDS-ExpA(max). CDS-ExpA(min) builds the smallest possible clusters while CDS-ExpA(max) builds the largest possible ones, reducing further the design space. Results show that CDS-ExpA(min) and CDS-ExpA(max) explore the design space 90% and 92% faster on average than a previously developed annealer-based exploration, method, at the expense of not finding 36% and 47% of the Pareto optimal designs and finding the smallest design that is 7% and 9% on average, larger, and the fastest design 28% and 32% slower, respectively.

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone finite state machine and that switches "contexts" consisting of many operational and storage units in processing elements (PEs) and wires between them. Utilizing the resources not only in two spatial dimensions but also vertically (time-multiplexed) under accurate timing and area constraints imposes challenges for a high-level synthesizer for the DRP. We describe a C-based behavioral synthesis method which features data path generation with clock speed optimization. This is achieved by including the overhead of selectors in the scheduling algorithm, and considering a wire delay at each PE level. A new technique is introduced to achieve high area efficiency. It works by effectively allocating multiple steps into the context. From the original highlevel synthesizer for application-specific integrated circuits, some of the basic rules such as operator and register sharing were completely changed due to the coarse grained and multi-context architecture. Experimental results show that the generated data paths are highly parallelized and well balanced between contexts. The delay controllability enables the highest throughput point to be found more easily.

Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.

Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.

Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

A practical solution to the complexity of design validation is semi-formal verification, where the specification of correctness criteria is done formally, as in model checking, but checking is done using simulation, which is guided by directed vector sequences derived from knowledge of the design and/or the property being checked. Simulation vectors must be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of our work is to generate property-specific testbenches for guided simulation, that are targeted either at proving the correctness of a full CTL property or at finding a bug. This is facilitated by generation of a property-specific model, called a "witness graph", which captures interesting paths in the design. Starting from an initial abstract model of the design, symbolic model checking, pruning, and refinement steps are applied in an iterative manner, until either a conclusive result is obtained or computing resources are exhausted. The witness graph is annotated with, e.g., state or transition priorities before testbench generation. The overall testbench generation flow, and the iterative flow for witness graph generation are shown.

This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

This paper presents C-based behavioral hardware design environment. Initially, we discuss motivations of the design environment and the merits and demerits of the C language as a behavioral hardware language. The configuration of the environment of which main component is a behavioral synthesizer "Cyber", is presented. Then, we explain various aspects of the C-based design method using some design experiences for both control dominated circuits and data intensive circuits. Lastly, we summarize current status of our C-based design and discuss problems to diffuse C-based design method widely.

This paper presents a low-overhead controller-based power management technique that redesigns control logic to reconfigure the existing data path components under idle conditions so as to minimize unnecessary activity. Controller-based power management exploits the fact that though the control signals in a register-transfer level implementation are fully specified, they can be respecified under certain states/conditions when the data path components that they control need not be active. We demonstrate that controller-based power management is often better-suited to control-flow intensive designs than comparable conventional power management techniques such as operand isolation. We present an algorithm to perform power management through controller redesign that consists of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and relabeling the activity graph resulting in redesign of the corresponding control expressions. We provide a comprehensive analysis of the potential side effects of controller-based power management on circuit delay, glitching activity at control and data path signals, and formation of false combinational cycles. Our algorithm avoids the above negative effects of controller-based power management to maximize power savings and minimize overheads. We present experimental results which demonstrate that (1) controller-based power management results in large power savings at minimal overheads for control-flow intensive designs, which pose several challenges to conventional power management techniques and (2) it is important to consider the various potential negative effects while performing controller-based power management in order to obtain maximal power savings.

This paper presents a low-overhead controller-based powermanagement technique that re-specifies control signals to reconfigureexisting multiplexer networks and functional units to minimizeunnecessary activity. We demonstrate that conventional powermanagement techniques may often not be suited to control-flowintensive designs, and provide a comprehensive analysis of thepotential negative effects of power management on circuit delay,glitching activity at control and data path signals, and formationof false combinational cycles. We present techniques to performpower management through controller re-specification while avoidingthe above negative effects, and demonstrate the efficiency ofthe techniques through experiments.

This paper proposes a controller-based technique for minimizing switching activity in controller/data path circuits. Though the control signals in a register transfer level (RTL) implementation are fully specified, they can be respecified under certain states/conditions when the data path components that they control need not be active. Unlike techniques that insert extra circuitry like transparent latches, controller re-specification is a low-overhead technique that merely reconfigures existing multiplexer networks and functional units to minimize activity in the data path. Hence, it is well suited to control-flow intensive designs, where power consumption in multiplexer networks forms a major component of the total power consumption. Our controller re-specification algorithm consists of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. Application of the proposed technique to several RTL circuits demonstrated the ability to reduce the total (controller+data path) power consumption by up to 51.8% compared to the initial area-optimized implementations, with nominal area and delay overheads.

Abstract| This paper presents a novel method for logic minimization in large-scale multi-level networks.It accomplishes its great reductions on the basis of multi-signal implications and the relationships among these implications.Both are handled on a transitive implication graph, proposed in this paper, which realizes high-speed, high-quality minimization.This proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.

Presents a generalized Horner's scheme-based approach which enables that a large and important subclass of nonlinear computations, named feedback linear computations, is efficiently, maximally, and arbitrarily sped-up. The new class includes popular nonlinear polynomial Volterra filters and widely used LMS and RLS adaptive filters. The effectiveness and low overhead of the proposed techniques is illustrated on several designs.

We address the problem of considering debugging requirements during high level synthesis by providing low-cost hardware support and scheduling and assignment methods for ensuring controllability and observability of the user specified variables. Two key conceptually new design ideas that enable efficient debugging are developed: pipelining of debugging variables for improving their scheduling and assignment freedom and use of I/O buffers for improving resource utilization of I/O pins. The provably optimal bounds for the maximum cardinality of the set of controllable and observable variables for a given design specification are derived. A polynomial time complexity synthesis algorithm for achieving the bounds is developed. The minimization of hardware overhead gives rise to a combinatorial optimization problem which is solved using a non-greedy heuristic algorithm. The effectiveness of the proposed Design-for-Debugging approach is demonstrated on several examples.

A scheduling/allocation and control synthesis algorithm is presented. The proposed algorithm can achieve good resource sharing and synthesize an efficient control sequence for nested conditional branches as well as for straight-line codes. The condition vector concept is introduced to allow mutual exclusion to be detected among operators, and is used to produce more efficient control sequences. The condition vector concept is concerned with the handling of nested condition branches and can be used for other scheduling methods. Results obtained from several experiments indicate that the proposed algorithms are efficient and effective.>

This paper describes a knowledge-based placement technique for printed wiring boards (PWB's).