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Hervé A. Jamrozik

dblp:98/2046 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 60% Distributed systems · 27% Cloud and datacenter computing · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
global memory
0.021997
Managing Server Load in Global Memory Systems · SIGMETRICS 1997
Reducing Network Latency Using Subpages in a Global Memory Environment · ASPLOS 1996
Memory systems › cache management
cache replacement
0.011997
Managing Server Load in Global Memory Systems · SIGMETRICS 1997
Memory systems › memory management › virtual memory
remote memory paging
0.011996
Reducing Network Latency Using Subpages in a Global Memory Environment · ASPLOS 1996
Memory systems › memory management
virtual memory
0.011996
Reducing Network Latency Using Subpages in a Global Memory Environment · ASPLOS 1996
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management
0.011997
Managing Server Load in Global Memory Systems · SIGMETRICS 1997
Parallel and multicore computing
load balancing
0.011997
Managing Server Load in Global Memory Systems · SIGMETRICS 1997

Methods — techniques the papers use, named apart from their topics

trace-driven simulation · 0.0queueing network model · 0.0subpage transfer · 0.0
YearPublicationVenuePosition
1997 Managing Server Load in Global Memory Systems
abstract
New high-speed switched networks have reduced the latency of network page transfers significantly below that of local disk. This trend has led to the development of systems that use network-wide memory, or global memory, as a cache for virtual memory pages or file blocks. A crucial issue in the implementation of these global memory systems is the selection of the target nodes to receive replaced pages. Current systems use various forms of an approximate global LRU algorithm for making these selections. However, using age information alone can lead to suboptimal performance in two ways. First, workload characteristics can lead to uneven distributions of old pages across servers, causing increased contention delays. Second, the global memory traffic imposed on a node can degrade the performance of local jobs on that node.This paper studies the potential benefit and the potential harm of using load information, in addition to age information, in global memory replacement policies. Using an analytic queueing network model, we show the extent to which server load can degrade remote memory latency and how load balancing solves this problem. Load balancing requests can cause the system to deviate from the global LRU replacement policy, however. Using trace-driven simulation, we study the impact on application performance of deviating from the LRU replacement policy. We find that deviating from strict LRU, even significantly for some applications, does not affect application performance. Based upon these results, we conclude that global memory systems can gain substantial benefit from load balancing requests with little harm from suboptimal replacement decisions. Finally, we illustrate the use of the intuition gained from the model and simulation experiments by proposing a new family of algorithms that incorporate load considerations as well as age information in global memory replacement decisions.
Geoffrey M. Voelker, Hervé A. Jamrozik, Mary K. Vernon, Henry M. Levy, Edward D. Lazowska
SIGMETRICS2
1996 Reducing Network Latency Using Subpages in a Global Memory Environment
abstract
New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Because pages are the fundamental transfer and access units in remote memory systems, page size is a key performance factor. Recently, page sizes of modern processors have been increasing in order to provide more TLB coverage and amortize disk access costs. Unfortunately, for high-speed networks, small transfers are needed to provide low latency. This trend in page size is thus at odds with the use of network memory on high-speed networks.This paper studies the use of subpages as a means of reducing transfer size and latency in a remote-memory environment. Using trace-driven simulation, we show how and why subpages reduce latency and improve performance of programs using network memory. Our results show that memory-intensive applications execute up to 1.8 times faster when executing with 1K-byte subpages, when compared to the same applications using full 8K-byte pages in the global memory system. Those same applications using 1K-byte subpages execute up to 4 times faster than they would using the disk for backing store. Using a prototype implementation on the DEC Alpha and AN2 network, we demonstrate how subpages can reduce remote-memory fault time; e.g., our prototype is able to satisfy a fault on a 1K subpage stored in remote memory in 0.5 milliseconds, one third the time of a full page.
Hervé A. Jamrozik, Michael J. Feeley, Geoffrey M. Voelker, James Evans II, Anna R. Karlin, Henry M. Levy, Mary K. Vernon
ASPLOS1