We present the cycle-time aware architecture synthesis methodology used in PICO-NPA that automatically synthesizes minimal cost RT-level designs from high-level specifications to meet a given cycle-time. This allows subsequent physical synthesis to succeed on first pass with predictable performance. The core of the methodology is a static timing analysis engine that is used at multiple levels - program-level, architecture-level and RT-level - in order to identify, schedule and validate useful operator chains that are incorporated into the design automatically. We present architecture synthesis results for several embedded applications and evaluate the benefits of this technique.

Published research on path delay fault (PDF) testing has largely focused on the PDF classification and test-vector generation problems. Little attention has been paid to the diagnosis of delay faults and in defining realistic metrics for delay-fault coverage, We present a statistical diagnosis framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay-fault tests. Under a model where distributed fabrication-process perturbations contribute to the occurrence of delay faults, we also find the associated likely fabrication-process parameter deviations from their nominal values as part of the diagnosis framework. We present results of experiments performed on some International Symposium on Circuits and Systems 1989 (ISCAS'89) benchmark circuits and also relate the slack of a path segment to its probability of contributing to the circuit failure. We also quantify the diagnosability of a PDF for a test and develop a methodology based on our statistical diagnosis framework to determine the diagnosability of each PDF detected by a given test set. We apply this approach to find the diagnosability of robust PDFs for the ISCAS'89 benchmark circuits. Furthermore, we propose a new and realistic definition of delay-fault coverage based on the percentage of fabricated faulty chips that can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay-fault sizes caused by the chip manufacturing process as opposed to previously defined metrics that have been based primarily on the percentage of faults tested. We present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of PDFs caused by distributed fabrication-process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between PDF coverage estimates for robust test sets obtained using our realistic definition and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We prove that the maximum primitive PDF delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. From this result, we devise a method to perform timing analysis based on primitive PDF identification which delinks functional analysis from delay computation. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re-identified due to component delay speedup (e.g., post-layout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.

We present a novel timing analysis mechanism which is based on identifying primitive path delay faults (primitive PDFs) in a circuit. We show that this approach gives the exact maximum delay of the circuit under the floating mode of operation assumption. Our timing analysis approach provides a framework where component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects can be handled very accurately. Under these effects, timing analysis using previously reported floating mode timing analyzers, e.g., viability, TrueD-F etc., is very pessimistic. Our timing analysis approach based on primitive PDF identification is also more efficient than conventional floating mode path sensitization analysis mechanisms in situations where critical paths need to be re-identified due to component delay speedup (e.g., postlayout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.

In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay fault sizes caused by fabrication process effects, as opposed to previously defined metrics which have been based primarily on the percentage of faults tested. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of path delay faults caused by distributed fabrication process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between distributed path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

Published research on delay fault testing has largely focused on generating a minimal set of test vector pairs to detect as many delay faults in a circuit as possible. Little regard has been paid to the diagnosability of delay faults in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. In an earlier work [1996] we presented a framework to detect which paths are likely to have caused a chip failure for a set of delay fault tests, and to find the associated likely fabrication process parameter variations. Here, we quantify the diagnosability of a path delay fault for a test, and develop a methodology based on the diagnosis framework presented earlier to determine the diagnosability of each path delay fault detected by a given test set. Furthermore, we apply this approach to find the diagnosability of robust path delay faults for the ISCAS'89 benchmark circuits.

Previous research in the field of path delay fault test generation has concentrated on finding tests which test paths regardless of component delay values. Coverage of such tests on benchmark circuits has been shown to be poor so we present a mechanism wherein path delay fault tests are found under the assumption of component delay variations resulting from fabrication process fluctuations. Component delay fault models are built which incorporate fabrication process effects represented in terms of basic process parameter variations. We use a sensitization approach based on signal stabilizing times to get conditions on primary inputs and path delays for which a delay fault is produced at the circuit outputs. A minimal test set is then extracted from these conditions. Results for the ISCAS'89 and Logic synthesis'91 benchmark circuits indicate the feasibility of this approach.