Pre-training large language models (LLMs) in data centers (DCs) is a complex yet essential task that requires vast computational resources and carefully designed infrastructures to enable efficient, large-scale distributed learning.However, without effective load balancing in RDMA over Converged Ethernet (RoCE) networks, network congestion and latency can create significant bottlenecks, disrupting data transmission, reducing resource utilization, and prolonging training times, ultimately compromising the scalability and performance of LLM training.To address these challenges, we propose and develop an innovative and cost-effective joint Device-Network Load Balancing (DNLB) approach.Built on our custom collective communication library, CTCCL, DNLB

The palindromic tree (a.k.a. eertree) is a data structure that provides access to all palindromic substrings of a string. In this paper, we propose a dynamic version of eertree, called double-ended eertree, which supports online operations on the stored string, including double-ended queue operations, counting distinct palindromic substrings, and finding the longest palindromic prefix/suffix. At the heart of our construction, we identify a new class of substring occurrences, called surfaces, that are palindromic substring occurrences that are neither prefixes nor suffixes of any other palindromic substring occurrences, which is of independent interest. Surfaces characterize the link structure of all palindromic substrings in the eertree, thereby allowing a linear-time implementation of double-ended eertrees through a linear-time maintenance of surfaces.

From the experience of offloading the network function of elastic IP (EIP) gateway to programming protocol independent packet processors (P4) switches at the edge cloud, we analyze the challenges of limited on-chip resources and share our insights to ensure the gateway’s quality of service (QoS). In this paper, we propose the design of EIP traffic management based on a P4 virtual buffer (VBuf), which makes use of surplus throughput. The novel design is implemented entirely on the network data plane in P4 and combines the advantages of general traffic shaping (GTS) and committed access rate (CAR). Then, evaluation experiments are carried out to verify QoS improvements. Their results show that the proposed method can reduce local traffic jitter by 4X and local packet loss by 10X in comparison with CAR. Besides, the proposed method leads to smoother congestion window change for TCP traffic.

A key factor affecting the computational time of floating random walk (FRW) based capacitance extraction is the variance of underlying Monte Carlo (MC) sample of capacitance. For achieving a fixed accuracy of result, the number of walks executed is proportional to the variance of this underlying random variable. In this work, we study the way to reduce the variance of random variable in FRW method through some theoretical analysis. An FRW method with symmetric multiple-shooting (SMS) walks is proposed, which stems out Ns symmetric sub-walk paths from a same sample point on Gaussian surface (with Ns being 2, 4, 8 or 16). Theoretical analysis reveals that the method with SMS walks could reduce the number of walks compared to the FRW method with important sampling (IS) approach under some assumption, and thus runs faster even considering the increase of hops within a walk. Its benefits also include the reduction of sampling points on Gaussian surface, which shows large benefit when the sampling on a complex Gaussian surface is very costly. Numerical experiments on the parallel-plate structure have validated the correctness of the theoretical analysis on the variances. With test cases from IC and FPD design, the proposed method with SMS walks is compared with the method with IS approach and the method with both IS and stratified sampling (SS) approach. The results show that the proposed method with SMS walks runs in similar speed or much faster than the FRW method using the IS+SS scheme, with up to 10.1× speedup.

Floating metals are special conductors introduced into conductor structures by design for manufacturing (DFM). They bring difficulty to accurate capacitance simulation. In this work, we aim to accelerate the floating random walk (FRW) based capacitance simulation for structures with considerable amounts of general floating metals. We first discuss how the existing modified FRW is affected by the integral surfaces of floating metals and propose an improved placement of integral surface. Then, we propose a hybrid approach called incomplete network reduction to avoid random transitions trapped by floating metals. Experiments on structures from IC and FPD design, which involves multiple floating metals and single or multiple master conductors, have shown the effectiveness of the proposed techniques. The proposed techniques reduce the computational time of capacitance calculation, while preserving the accuracy.

IT services are now popularly hosted in cloud systems. In order to enhance the availability of cloud services, an emerging approach for detecting failures of cloud components is to monitor Key Performance Indicators (KPIs) of the components and apply Neural Network based AI technologies to detect KPI anomalies. Multivariate Time Series Anomaly Detection (TSAD) models have been designed for this purpose. However, when applying such models directly to real-world cloud systems the anomaly detection performance is not as good. This is because the number of KPIs in real cloud systems is typically much more than the number of KPIs in the datasets used for model evaluation, and the larger number of KPIs bring about a performance loss of the models’ anomaly detection. Therefore, selecting KPIs properly is essential for applying multivariant KPI data for any practical anomaly detection. This paper studies this performance loss issue when TSAD models are applied onto real-world cloud systems, and proposes fKPISelect, a mechanism of automated KPI selection based on fault injection. We implemented fKPISelect, deployed it to a real cloud system, and created a real-world KPI dataset. We conducted extensive experiments, and the experimental results show the effectiveness and practicality of fKPISelect: it improves the F1 score of anomaly detection from 0.68 to 0.91 for real-world KPI data.

Precharacterizing the transition cubes containing stratified dielectrics is inevitable for the floating random walk (FRW)-based capacitance extraction. Each multilayer-dielectric transition cube is characterized by a pair of Green’s function table (GFT) and weight value table (WVT), and all these GFTs and WVTs usually have large volume and constitute the major memory cost of the FRW algorithm. In this work, we explore the geometric symmetry of the multilayer-dielectric transition cube to enable volume reduction and fast generation of the GFT and WVT. For a general transition cube with stratified dielectrics and the one with four equal-thickness dielectrics, two schemes are proposed to reduce the volume of GFT and WVT by$8\times $and over$10\times $, respectively. Accordingly, an approach for fast generation of the reduced GFT/WVT is proposed, which is proved to produce the same result as the original GFT/WVT values. And, an improved FRW algorithm is proposed to utilize the reduced GFTs/WVTs without the sacrifice of runtime or accuracy. Both theoretical analysis and numerical experiments are conducted to demonstrate the remarkable volume reduction of precharacterization data (GFTs/WVTs). The fast GFT/WVT generation approach and the improved FRW algorithm are also validated with numerical experiments, showing over$10\times $speedup of the precharacterization process, and accurate and memory-efficient capacitance extraction as well.

As the feature size scales down, the process technology becomes more complicated and the design margin shrinks, accurate parasitic extraction during IC design is largely demanded. In this invited paper, we survey the recent advancements on parasitic extraction techniques, especially those enhancing the floating random walk based capacitance solver and incorporating machine learning methods. The work dealing with process variation are also addressed. After that, we briefly discuss the challenges for capacitance extraction under advanced process technologies, including manufacture-aware geometry variations and middle-end-of-line (MEOL) parasitic extraction, etc.

Capacitance extraction and power grid (PG) analysis for IC design involve large-scale numerical simulation problems. As the process technology becomes more complicated and design margin is shrinking, the capacitance field solver and power-grid matrix solver with high accuracy and capability for handing large and complex structure are highly demanded. In this invited paper, we present recent application of statistical and AI methods in these two fields. The Markov-chain model and relevant analysis are presented for developing an efficient technique for handling conformal dielectrics in the floating random walk based capacitance extraction. Then, two approaches reducing the computational cost of a domain decomposition based power-grid solver are presented. One employs supervised machine learning while the other is inspired by the A*-search algorithm.

In this paper, two techniques are proposed to enhance the floating random walk (FRW) based capacitance solver for handling non-stratified dielectrics in very large-scale integrated (VLSI) circuits. They follow an existing approach which employs approximate eight-octant transition cubes while simulating the structure with conformal dielectrics. Firstly, the symmetry property of the transition probabilities of the eight-octant cube is revealed and utilized to derive an on-the-fly sampling scheme during the FRW procedure. This avoids the pre-characterization, saves substantial memory, and improves computational accuracy for extracting the structure with non-stratified dielectrics. Then, the space management technique is extended to improve the runtime efficiency for simulating structures with thousands of non-stratified dielectrics. Numerical experiments are carried out to validate the proposed techniques and show their effectiveness for handling structures with conformal dielectrics and air bubbles. Moreover, the extended space management brings up to 1441X speedup for handling structures with from several thousand to nearly one million non-stratified dielectrics.

The idea of macromodel was recently proposed for encrypting sensitive structures and accelerating the floating random walk (FRW)-based capacitance extraction. In the existing work, boundary element method (BEM) is employed to generate the macromodel, which might cause large error due to the violation of macromodel's properties. To overcome this issue, we propose a modified finite difference method (FDM) with second-order electric field intensity formulas for generating the macromodel. It ensures the macromodel's properties and thus largely improves the reliability of the macromodel-aware FRW algorithm. The numerical experiments with 3-D structures have validated our theoretic analysis, and have shown the proposed technique reliably brings more accurate capacitance results than the BEM and conventional FDM.

A novel technique is proposed to deal with conformal dielectrics for extracting capacitances with floating random walk (FRW) method. It is based on the observation that the transition probabilities for the eight-octant cube exhibit a kind of symmetry and are closely related to those of a single-dielectric transition cube. We first theoretically proved this observation, and then proposed an approach generating the transition probabilities without any precalculation and memory cost. This enables on-the-fly sampling on eight-octant transition cubes and derives an improved FRW algorithm for capacitance extraction with conformal dielectrics. Compared with the existing approach, the proposed improved algorithm saves substantial memory cost and is more accurate. The numerical results have validated the theoretic analysis and demonstrated the benefits of the proposed capacitance solver for handling conformal dielectrics.