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Koichi Suda

dblp:98/3165 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 50% Parallel and multicore computing · 25% Performance modeling and evaluation · 25%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › concurrent system
multitasking
0.011993
Highly multi-tasking real-time systems and their evaluation · RTSS 1993
Embedded and real-time systems
real-time operating systems
0.011993
Highly multi-tasking real-time systems and their evaluation · RTSS 1993
Embedded and real-time systems
real-time scheduling
0.011993
Highly multi-tasking real-time systems and their evaluation · RTSS 1993

Methods — techniques the papers use, named apart from their topics

task scheduling · 0.0OS performance evaluation · 0.0
YearPublicationVenuePosition
1993 Highly multi-tasking real-time systems and their evaluation
abstract
Application systems in real-time processing fields, in addition to those systems whose most important requirement is to complete processing within a given response time, also include systems whose aims are to raise throughput within the response time restrictions, in which a high degree of multi-tasking is of primary importance. The paper makes proposals on task scheduling and OS functions in highly multi-tasking real-time processing domains, and outlines a research project presently being undertaken in NTT to study real-time OS performance evaluation methods geared to these domains.>
Terunao Soneoka, Ayaru Oizumi, Koichi Suda
RTSS3
1989 FPC: a floating-point processor controller chip for systolic signal processing
abstract
The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-b instruction word that provides concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams. The novel architectural features of the cell are described, and a matrix multiplication example is used to demonstrate their usefulness.>
Ross A. W. Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken
ICCD4