A true random number generator (TRNG) is proposed and evaluated by field-programmable gate arrays (FPGA) implementation that generates random numbers by exclusive-ORing (XORing) the outputs of many SR latches (Hata and Ichikawa, IEICE Trans. Inf. Syst. E95-D(2):426–436, 2012). This enables compact implementation and generates high-entropy random numbers. In this paper, we fabricate and evaluate 39 TRNGs using SR latches on 0.18 μ m ASICs. Random numbers are generated by XORing the outputs of 256 SR latches. Our TRNGs pass the SP800-90B health tests and the AIS20/31 statistical tests in changing temperatures (from −20 to 60 °C) and voltages (1.80 ± 0.15 V). We also perform an independent and identically distributed (IID) test and calculate min-entropy according to the SP800-90B. With these tests, we are able to confirm that our TRNGs are highly robust against environmental stress. The power consumption and circuit scale of our TRNGs are 0.27 mW and 1240.5 gates, respectively. Our TRNGs that use SR latches are small enough to be implemented in embedded devices.

Low uniqueness and vulnerability to machine-learning attacks are known as two major problems of Arbiter-Based Physically Unclonable Function (APUF) implemented on FPGAs. In this paper, we implement Double APUF (DAPUF) that duplicates the original APUF in order to overcome the problems. From the experimental results on Xilinx Virtex-5, we show that the uniqueness of DAPUF becomes almost ideal, and the prediction rate of the machine-learning attack decreases from 86% to 57%.

Arbiter-basedPhysically Unclonable Function (PUF) is one kind of the delay-based PUFs that use the time difference of two delay-line signals.One of the previous work suggests that Arbiter PUFs implemented on Xilinx Virtex-5 FPGAs generate responses with almost no difference, i.e. with low uniqueness.In order to overcome this problem, Double Arbiter PUF was proposed, which is based on a novel technique for generating responses with high uniqueness from duplicated Arbiter PUFs on FPGAs.It needs the same costs as 2-XOR Arbiter PUF that XORs outputs of two Arbiter PUFs.Double Arbiter PUF is different from 2-XOR Arbiter PUF in terms of mode of operation for Arbiter PUF: the wire assignment between an arbiter and output signals from the final selectors located just before the arbiter.In this paper, we evaluate these PUFs as for uniqueness, randomness, and steadiness.We consider finding a new mode of operation for Arbiter PUF that can be realized on FPGA.In order to improve the uniqueness of responses, we propose 3-1 Double Arbiter PUF that has another duplicated Arbiter PUF, i.e. having 3 Arbiter PUFs and output 1-bit response.We compare 3-1 Double Arbiter PUF to 3-XOR Arbiter PUF according to the uniqueness, randomness, and steadiness, and show the difference between these PUFs by considering the mode of operation for Arbiter PUF.From our experimental results, the uniqueness of responses from 3-1 Double Arbiter PUF is approximately 50%, which is better than that from 3-XOR Arbiter PUF.We show that we can improve the uniqueness by using a new mode of operation for Arbiter PUF.

Abstract—Physically Unclonable Function (PUF) is expected to be an innovation for anti-counterfeiting devices for secure ID generation, authentication, etc. In this paper, we propose novel methods of evaluating the difficulty of predicting PUF responses (i.e. PUF outputs), inspired by well-known differential and linear cryptanalysis. According to the proposed methods, we perform a first third-party evaluation for Bistable Ring PUF (BR-PUF), proposed in 2011. The BR-PUFs have been claimed that they have a resistance against the response predictions. Through our experiments using FPGAs, we demonstrate, however, that BR-PUFs have two types of correlations between challenges and responses, which may cause the easy prediction of PUF responses. First, the same responses are frequently generated for two challenges (i.e. PUF inputs) with small Hamming distance. A number of randomly-generated challenges and their variants with Hamming distance of one generate the same responses with the probability of 0.88, much larger than 0.5 in ideal PUFs. Second, particular bits of challenges in BR-PUFs have a great impact on the responses. The value of responses becomes ‘1 ’ with the high probability of 0.71 (> 0.5) when just particular 5 bits of 64-bit random challenges are forced to be zero or one. In conclusion, the proposed evaluation methods reveal that BR-PUFs on FPGAs have some correlations of challenge-response pairs, which helps an attacker to predict the responses. I.

To guarantee Quality of Service(QoS) for real-time applications strictly, we have proposed an output buffer control mechanism in IP routers, confirmed its effectiveness through simulations and implemented a prototype. This mechanism can guarantee QoS strictly within single router. In this paper, we propose the control scheme of mutual cooperation between IP routers equipped with the above-mentioned mechanism by using one of the signaling protocols. Our proposed scheme aims to stabilize End-to-End (E2E) delay of a flow within target delay. Also, reserved resources are dynamically updated between IP routers with our mechanism to improve E2E packet loss rate. We perform the implemental design of our scheme and empirical evaluation through the implementation. As one of results, we validated quantitatively that our scheme improves the quality of video picture.

Various real-time applications are widely used with the development of network infrastructure. To guarantee QoS(Quality of Service) of these applications strictly, the Internet will require a flow-based priority control. Thus, we have proposed an output buffer control mechanism. In this paper, to guarantee End-to-End QoS maximally by exploiting the buffer control mechanism, we propose the method of mutual cooperation between IP routers equipped with our mechanism by using one of the signaling protocols. In addition, we show the effectiveness of our proposal by computer simulation.