EDBT 2026 Demo / reviewers in the wild / expert
Huiyu Feng
dblp:98/373
· DBLP profile ↗
6ranked-venue papers
3as first author
4since 2021 · last 2026
0009-0004-7313-7224ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 2 since 2021Computer networks · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Physical-layer communications · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 44% GPUs and heterogeneous computing · 44% High-performance computing · 13% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Physical-layer communications › modulation
line coding |
1.0 | 1 | 2026 | Enhanced 8B/6T Line Coding Design for High-Reliability Data Communication · IEEE Trans. Commun. 2026 |
Performance modeling and evaluation
benchmarking |
0.2 | 1 | 2013 | An early performance evaluation of many integrated core architecture based SGI rackable computing system · SC 2013 |
High-performance computing
performance optimization at scale |
0.0 | 1 | 2013 | An early performance evaluation of many integrated core architecture based SGI rackable computing system · SC 2013 |
Methods — techniques the papers use, named apart from their topics
microbenchmarks · 0.2OpenMP · 0.2NAS Parallel Benchmarks · 0.2MPI · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A High-Performance and Hardware-Efficient Iterative Detection and Decoding Receiver for Polar-Coded Massive MIMO SystemabstractPolar-coded massive multiple-input multiple-output (MIMO) systems have attracted significant attention in wireless communications due to their superior performance with iterative detection and decoding (IDD). However, the practical implementation of polar-coded IDD receivers faces two critical challenges: the high computational complexity of massive MIMO detection and the difficulty in pursuing low-complexity and high-performance soft-output polar decoding. In this paper, we propose a comprehensive system design to address both challenges. For detection, we propose a vectorized Gauss-Seidel (VGS) detector supporting soft-input and soft-output (SISO) operations, achieving$2\times $higher hardware efficiency than existing works when implemented on FPGA. For decoding, we develop a partial-sum-based soft-output successive cancellation list (PS-SSCL) decoder that generates soft outputs without additional decoding procedures. Compared to state-of-the-art soft-output list (SOL) decoders, the PS-SSCL reduces memory usage by 55% and computational complexity by 62% while providing an extra 0.3 dB gain in IDD systems. Finally, an interleaved IDD receiver integrating the SISO VGS detector and PS-SSCL decoder is coded with RTL and synthesized under TSMC 28-nm CMOS technology, achieving an extra coding gain of 1.5 dB at FER$= 10^{-3}$over conventional separate detection and decoding (SDD) receiver with only 5% sacrifice in area efficiency. Huiyu Feng, Suwen Song, Chuan Zhang 0001, Zhongfeng Wang 0001 |
IEEE Trans. Circuits Syst. I Regul. Pap. | 1 |
| 2026 | Enhanced 8B/6T Line Coding Design for High-Reliability Data Communication
Huiyu Feng, Suwen Song, Zhongfeng Wang 0001 |
IEEE Trans. Commun. | 1 |
| 2024 | Efficient Soft-Output List Decoding of Polar Codes for Iterative Detection and Decoding in MIMO SystemabstractPolar-coded multiple-input multiple-output (MIMO) system has obtained increasing attention recently, in which iterative detection and decoding (IDD) brings improved performance compared to separate detection and decoding (SDD) schemes. IDD requires the exchange of soft information between the detector and decoder, but the best-performing decoding algorithm for polar codes, the cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) algorithm, cannot generate soft outputs by itself. To address this issue, existing high-performance soft-output decoders combine the CA-SCL decoder with the belief propagation (BP) or soft cancellation (SCAN) decoding process to generate soft outputs, leading to high computational complexity and memory requirements. In this work, an efficient partial sum-based soft-output SCL (PS-SSCL) decoder is proposed, which utilizes the inherent partial sums generated during the CA-SCL decoding process to calculate soft outputs without introducing any additional decoding procedure. For the 5G (256,128) polar code, the proposed PS-SSCL decoder achieves a 57% reduction in memory requirements and a 62% reduction in computational complexity compared to the state-of-the-art soft-output list (SOL) polar decoder. Additionally, the PS-SSCL decoder can also bring more than 0.2 dB gain over the SOL decoder, when integrated into the IDD receiver with the linear minimum mean square error (LMMSE) detector. Huiyu Feng, Suwen Song, Zhongfeng Wang 0001 |
PIMRC | 1 |
| 2024 | Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO SystemsabstractThe expectation propagation (EP) algorithm is near-optimal in massive multiple-input multiple-output (MIMO) systems but suffers from high computation complexity. Most of the previous works exploit the channel hardening property and introduce iterative matrix inversion algorithms to simplify the EP algorithm, but the performance degrades dramatically in non-ideal channels. In this paper, we propose a more universal EP-based detector, which can perform well in both ideal and non-ideal channels. Firstly, two general methods are proposed to effectively improve the detection performance and convergence speed of iterative matrix inversion algorithms under correlated channels. The proposed diagonal preprocessing (DP) method can improve the detection performance by more than 2-dB compared to not using this method; the novel eigenvalue parameter estimation method guarantees the convergence of all the frames. These two methods are applied to the second-order Richardson iteration (SORI) algorithm to derive the DP-SORI algorithm, which converges more than twice as fast as the state-of-the-art design. Secondly, for another important part of EP-based algorithms, namely the calculation of expectation and variance, complicated operations such as exponentiations, divisions, and inversions are all removed by algorithmic optimization. Moreover, based on the proposed approximate EP with DP-SORI (EPA-DP-SORI) algorithm, an efficient hardware design is developed, combining multiple optimization methods such as efficient matrix multiplication architecture design and low-complexity LDL decomposition. In addition to better detection performance compared with the state-of-the-art design, the presented EPA-DP-SORI detector can also deliver$1.27 \times $and$1.57 \times $higher area and energy efficiency. Yangyang Chen 0005, Huiyu Feng, Suwen Song, Zhongfeng Wang 0001 |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2013 | An early performance evaluation of many integrated core architecture based SGI rackable computing systemabstractIntel recently introduced the Xeon Phi coprocessor based on the Many Integrated Core architecture featuring 60 cores with a peak performance of 1.0 Tflop/s. NASA has deployed a 128-node SGI Rackable system where each node has two Intel Xeon E2670 8-core Sandy Bridge processors along with two Xeon Phi 5110P coprocessors. We have conducted an early performance evaluation of the Xeon Phi. We used microbenchmarks to measure the latency and bandwidth of memory and interconnect, I/O rates, and the performance of OpenMP directives and MPI functions. We also used OpenMP and MPI versions of the NAS Parallel Benchmarks along with two production CFD applications to test four programming modes: offload, processor native, coprocessor native and symmetric (processor plus coprocessor). In this paper we present preliminary results based on our performance evaluation of various aspects of a Phi-based system. Subhash Saini, Haoqiang Jin, Dennis C. Jespersen, Huiyu Feng, M. Jahed Djomehri, William Arasin, Robert Hood, Piyush Mehrotra, Rupak Biswas |
SC | 4 |
| 2010 | SPEC MPI2007 - an application benchmark suite for parallel systems using MPIabstractAbstract The SPEC High‐Performance Group has developed the benchmark suite SPEC MPI2007 and its run rules over the last few years. The purpose of the SPEC MPI2007 benchmark and its run rules is to further the cause of fair and objective benchmarking of high‐performance computing systems. The rules help to ensure that the published results are meaningful, comparable to other results, and reproducible. MPI2007 includes 13 technical computing applications from the fields of computational fluid dynamics, molecular dynamics, electromagnetism, geophysics, ray tracing, and hydrodynamics. We describe the benchmark suite, and compare it with other benchmark suites. Copyright © 2009 John Wiley & Sons, Ltd. Matthias S. Müller, Matthijs van Waveren, Ron Lieberman, Brian Whitney, Hideki Saito 0001, Kalyan Kumaran, John Baron, William C. Brantley, Chris Parrott, Tom Elken, Huiyu Feng, Carl Ponder |
Concurr. Comput. Pract. Exp. | 11 |