This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28nm FDSOI prototype chip of a 100$\times $4 compute array that shows a 15.8TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100$\times $100 computing units leads to a 99.2TOPS/W energy efficiency.

This paper presents a novel architecture of a SAR assisted 2 step ADC where the SAR residue is quantized with a bidirectional digital slope time-based converter. The bidirectional slope halves the conversion time of the second stage. Furthermore, the redundancy requirements in the second stage are considerably reduced through a unified global calibration scheme. A practical example is given for a 12-bit 64 MS/s ADC with 67 dB SNDR and$\mathbf{208}\ \boldsymbol{\mu} \mathbf{W}$estimated power consumption targeted at ultra-low power RF receivers. The complete architecture including calibration has been validated with VerilogA models including capacitor mismatch, comparator offsets and noise.

Sensor Networks (SN) could be defined as networks of autonomous devices that can sense and/or act on physical or environmental conditions cooperatively. In sensor networks, data is typically sensed and sent toanaggregator thatwill process it with local AI or send it to a cloud with larger AI. This centralized architecture has drawbacks such as the aggregator having to receive and process a potentially huge amount of data, which results in power consumption that can be significant. In addition, the transmission of all the sensor data results in extra consumption of energy due to communication. To reduce the impact of this last point, on-edge computing allows data to be pre-processed at the sensor level. It is often used in the architecture of distributed sensor networks in which each node receives data from other nodes in the network and processes it with its local data. In this work, a distributed sensor network model aims to solve this problem while reducing the impact of data transmission on energy consumption. The proposed model is able to reduce the number of transmitted bits per node by 90% in a node-to-node directed communication scenario. It is also capable of working with different AI paradigms depending on the required balance between energy consumption, application configurability, and accuracy. Finally, this model is capable of converging even in a network without complete interconnections between nodes.

In this paper, we propose a methodology for upscaling fractional vegetation cover (FVC) estimates derived from unmanned aerial vehicles (UAVs) to a larger area using freely available Sentinel-1/2 and Landsat-8 satellite data in the semi-arid Nama-Karoo biome of South Africa. To the best of our knowledge, such an approach is still lacking yet critical for understanding human-environment interactions, degradation, and the impacts of climate change in this vulnerable dryland ecosystem. The proposed approach utilizes ultra-high spatial resolution UAV imagery (i.e. <; 5 cm) to develop a high quality FVC product. The resulting product is then used to upscale and validate satellite-based estimates of FVC. The rationale for upscaling UAV estimates to the satellite-scale is not only to cover larger areas but also to exploit historical satellite time-series data, in an attempt to understand past trends and vegetation dynamics in the Nama Karoo-Grassland ecotone. The proposed method is expected to produce the first-ever high-resolution continuous maps of FVC and its changes in the above-mentioned ecosystem. Such information is of vital importance as it could help decision makers to gain a better understanding of the extent at which mechanisms such as bush encroachment, grassland expansion, or degradation are occurring in dryland ecosystems.

Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined with a puncture-based communication method are introduced. Theoretical models of the hardware blocks are presented, outlining the impact of their specifications on the system. Moreover, we evaluate the synchronization efficiency in simulation and compare with a duty-cycled receiver topology. Improvement in power consumption of at least 26% and tight latency control are highlighted at no cost on the channel availability.

The design of a baseband decision feedback equalizer, featuring a continuous-time digital delay line, is discussed within the context of a wireless, Line-Of-Sight, communication scenario over the 60-GHz band. BER simulations advocate for a critical-tap cancellation scheme, which leads to the realization of an equalizer featuring a small number of taps. A two-step configurable architecture is suggested as the equalizer's feedback path, in order to mitigate the loss of robustness that is caused by the absence of the clock. Simulations reveal the system's channel-dependent power consumption character and a delay line power consumption reduction of 3 to 4 times, when compared with its clocked counterpart.

This paper presents a 60GHz heterodyne receiver architecture with IF sub-sampling. A particular arrangement of the frequency plan allows anti-alias filtering by the charge-domain subsampler. Down-conversion, channel filtering and IQ demodulation are merged into a unique operator without any extra cost in terms of area and power consumption. The proposed architecture is able to receive up to 4 bonded channels and complies with the requirements of the standards for 60GHz wireless communications. The result of this study shows that subsampling is a good candidate for low power and configurable receivers for mmW wireless communications.

This paper presents a transmitter architecture able to manage its spurious emissions over a wide bandwidth. The architecture is based on a multiple-path polar transmitter with digital power amplifiers (DPA). The paths work at different sample rates, thus producing spectral images located at different frequencies. This multirate implementation generates more spurious images than conventional architectures, but with reduced image power. This leads to a significant signal-to-spurious improvement over a wide bandwidth. Using the proposed architecture in a transmitter targeting LTE standard, the spurious emissions are reduced by 20dB over a frequency band from 800MHz to 3GHz, allowing to remove any analog filter stages to respect the standard specifications.

A 4× oversampling 18thorder digital FIR filter suitable to replace all analog baseband filters in a mobile high-data-rate wireless communication transmitter is presented. Special architecture optimizations allow an estimated output sampling rate of 10Gs/s in 65nm CMOS while respecting full spectrum mask specifications of the ECMA & IEEE standards over the radio band of 8 GHz.

This paper presents the complete design methodology of a very low-voltage /spl Delta//spl Sigma/ third-order modulator from high-level specifications down to layout. Behavioral models taking into account cell nonidealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover the same design knowledge has been successfully reused in another fourth-order modulator.

The design of a wireless micro-robot is investigated. The robot consists of a distributed ciliary micro-motion system with electrostatic actuation. Two new types of 150/spl times/100 /spl mu/m/sup 2/ actuators have been fabricated thanks to a three-level polysilicon process. Remote powering is achieved by inductive coupling at 13.56 MHz. A simple analytical model for the inductive coupling is developed. A 24-/spl mu/m thick electroplated gold antenna has been optimized, then fabricated on an epoxy film in order to obtain a light component supported by the robot. Electronics for the transceiver and the robot control are also presented.

For the past few years, the mobile phone market has been facing fast growth. However, the first generations of mobile telecommunications were based on several different standards over the world, and even at the time major operators negotiate for the third generation licenses, it seems UMTS, CDMA2000 and TD-SCDMA cannot achieve one single standard. A great challenge would be to develop flexible, re-configurable mobile phone handsets that could switch from one standard to another. To do so, MEMS technology is expected as a promising solution to provide tiny, low-consumption tunable components. Moreover, enhancing MEMS technologies to be compatible with IC processing, a novel architecture can be used for a MEMS-based transceiver that could reach the ultimate goal of a fully-integrated single-chip system. Indeed, it has been recently demonstrated that every off-chip, bulky, and expensive passive component present in a typical superheterodyne transceiver front-end could be advantageously replaced by an RF-MEMS counterpart. For example, micro-mechanical resonators could avoid the use of ceramic, SAW, and quartz off-chip resonators to allow low-loss filtering, mixing and carrier generation. But that kind of micro-scale resonators requires high quality factor and temperature stability to achieve highly selective filtering and low phase-noise frequency references. So, to demonstrate this ability, resonators and filters with center frequency up to 300 MHz were designed, and for their fabrication, two processes have been undertaken: an epitaxial thick-film polysilicon industrial technology and a thin-film polysilicon-based technology made compatible with a CMOS-SOI technology.

A fully differential opamp suitable for very-low voltage switched-capacitor circuits in standard CMOS technologies is introduced. The proposed two stage opamp needs a simple low voltage CMFB switched-capacitor circuit only for the second stage. Due to the reduced supply voltage, the CMFB circuit is implemented using boot-strapped switches. Minor modifications allow to use chopper stabilization for flicker noise reduction. Two different compensation schemes are discussed and compared using an example for 1 V operation of the amplifier.

The switched current circuit technique allows mixed-signal integrated circuits including data-converters and filters to be fabricated in a conventional CMOS process. ASIMOV, described in this paper, is a computer-aided design tool to support the systematic design of such circuits. It is capable of topology selection and sizing of current memory cells from a set of user specifications, Analytical models, coupled with numerical optimization guided by a heuristic rule-base, are used for fast response time. Models for the most commonly used cells are implemented.

In switched current circuits, the clock frequency is limited by the maximum tolerable error. This paper presents a simple but accurate model for the settling behaviour of current memory cells. It is suitable for implementation in discrete-time simulators or synthesis tools, and requires far less computing time than a complete SPICE simulation, while giving comparable accuracy. The proposed model relies on a piece-wise linear description of the memory transistor's transconductance, and a precise modelling of the cell behaviour during the non-overlap of the sampling clocks. Both SPICE simulation and experimental results are compared to the new model.>