EDBT 2026 Demo / reviewers in the wild / expert
Richard N. Zucker
dblp:98/4152
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 88% Parallel and multicore computing · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory consistency
memory consistency model |
0.0 | 1 | 1992 | A Performance Study of Memory Consistency Models · ISCA 1992 |
Memory systems › memory consistency › memory consistency model
weak memory model |
0.0 | 1 | 1992 | A Performance Study of Memory Consistency Models · ISCA 1992 |
Memory systems › cache
cache miss |
0.0 | 1 | 1992 | A Performance Study of Memory Consistency Models · ISCA 1992 |
Parallel and multicore computing
multiprocessor system |
0.0 | 1 | 1992 | A Performance Study of Memory Consistency Models · ISCA 1992 |
Methods — techniques the papers use, named apart from their topics
performance simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | A Performance Study of Memory Consistency ModelsabstractRecent advances in technology are such that the speed of processors is increasing faster than memory latency is decreasing. Therefore the relative cost of a cache miss is becoming more important. However, the full cost of a cache miss need not be paid every time in a multiprocessor. The frequency with which the processor must stall on a cache miss can be reduced by using a relaxed model of memory consistency. Richard N. Zucker, Jean-Loup Baer |
ISCA | 1 |
| 1991 | On Synchronization Patterns in Parallel Programs
Jean-Loup Baer, Richard N. Zucker |
ICPP (2) | 2 |