In spite of using scan designs, there remain serious problems concerning the generation and confirmation of test vectors for potential timing problems. Most of the available test generators and the only fault simulators reported for path-delay faults in scan designs rely upon the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. This paper describes a path-delay fault simulator for standard scan environments, based on the parallel-pattern-single-fault-propagation technique.>

Fastpath generates non-robust, robust or single-path-sensitization hazard-free robust path-delay tests for standard scan designs including high-impedance elements and functionally-described blocks. Results show effective and memory-efficient operation.

As CAD tools become more sophisticated, they can synthesize logic netivorks that more nearly optimize the circuit area resources to maximize operating speeds.In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the m"mum delay through the network (cycle time).The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptim"zed designs.Finally, recommendations will be made on how network tim"ng optimization can be abne in such a way as to minimize the adverse impact on product yield.

As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.

It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test.>

A high-speed fault simulator is presented that combines demand-driven simulation techniques with a bit-encoded deductive fault simulation scheme. The simulator uses an efficient approach to the management of signal value and fault list structures intended to minimize disk thrashing during execution. Input cone analysis is used during preprocessing to identify gates with independent inputs so that optimized evaluation routines that include early cutoff can be used. Results are given for the demand-driven deductive fault simulator and contrasted with an earlier demand-driven parallel fault simulator.>