Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.

Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a design's multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.

An interesting property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as long as it can "borrow" time from the shorter paths in the subsequent logic stages. This gives designers a lot of flexibility in designing circuits, especially high performance ones. However, it also increases the complexity in timing analysis. Finding the best clock period or determining how much time to borrow from the subsequent logic stages is difficult especially for designs containing multiple clocks, mixed-clock paths, user-specified multicycle paths, and false paths. In this article, we formulate the time borrowing problem as a linear programming problem. An optimal time borrowing solution can be found by solving the formulation. Based on this time borrowing solver, algorithms are proposed for timing optimization to achieve the optimal clock period. Experimental results show our algorithm is efficient and yields very good results.

Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 /spl mu/m. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental results show that this algorithm provides better result after detail routing is completed.

Article Free Access Share on Post-routing timing optimization with routing characterization Authors: Chieh Changfan Computer Science Dept. University of California, Riverside and Avant! Corporation, 46871 Bayside Parkway, Fremont, CA Computer Science Dept. University of California, Riverside and Avant! Corporation, 46871 Bayside Parkway, Fremont, CAView Profile , Yu-Chin Hsu Avant! Corporation, 46871 Bayside Parkway, Fremont, CA Avant! Corporation, 46871 Bayside Parkway, Fremont, CAView Profile , Fur-Shing Tsai Avant! Corporation, 46871 Bayside Parkway, Fremont, CA Avant! Corporation, 46871 Bayside Parkway, Fremont, CAView Profile Authors Info & Claims ISPD '99: Proceedings of the 1999 international symposium on Physical designApril 1999 Pages 30–35https://doi.org/10.1145/299996.300013Published:12 April 1999Publication History 0citation212DownloadsMetricsTotal Citations0Total Downloads212Last 12 Months19Last 6 weeks6 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The STAR package consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The data structures are created and the lower limit of each area-dominant resource is determined in the preprocessing phase. In the DPC phase, the allocation is vertically divided into three subtasks: data transfer binding, operation assignment, and variable binding. Data transfers, operations and variables are grouped into clusters of manageable size, and a branch-and-bound search is performed in each cluster for each subtask. In the DPR phase, the data path is refined globally by evaluating the binding quality of each object. The contributions include: (1) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources in which the object uses; (2) a method to judge the potential for upgrading a data path; and (3) an iterative improvement technique based on the idea of a relation network and state transition.>

A system is described for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The actions taken in each phase are described. The authors' contributions include the following: (1) theorems for the lower bound of the number of interconnections; (2) in the DPR phase, a more global view of the allocation problem is taken by ripping up and reallocating different types of objects simultaneously; (3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; (4) a method to judge the potential for upgrading a data path; and (5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results.>

A general-purpose routing algorithm for very-large-scale integrated (VLSI) circuits and printed circuit board (PCB) designs is proposed. Ideas behind the maze-running algorithm and the hierarchical routing algorithm are combined into a powerful algorithm called hybrid routing. The new algorithm demonstrates a speed compatible to a hierarchical router and produces routings with quality equivalent to that obtained by a maze router. Hybrid routing is based on the maze-running method with a third search dimension added. The extra search space is built by recursively constructing a hierarchy of coarser grid meshes. By means of a parameter-controlled expansion into the coarser meshes, the hybrid router is able to find the preferred search region very quickly and will not miss local information as a hierarchical router does. A user-given parameter can turn the algorithm into a pure maze router, a pure hierarchical router, or a wide spectrum of hybrid routers with different speed/quality characteristics between the extremes. The algorithm has been implemented and integrated into a global router that can handle large-scale routing, such as that encountered in the sea-of-gates layout.>

A general-purpose routing algorithm is proposed. Ideas behind both the maze-running algorithm and the hierarchical routing algorithm are combined into a hybrid routing algorithm. The new algorithm demonstrates a speed compatible to a hierarchical router and produces routings with quality equivalent to that by a maze router. Hybrid routing is based on the maze-running method with a third search dimension added. The extra search space is built by recursively constructing a hierarchy of coarser grid meshes. A user-given parameter can turn this algorithm into a pure maze router, a pure hierarchical router, or a wide spectrum of hybrid routers with different speed/quality characteristics between the extremes. With this approach, it is possible to handle easily a routing of large size, such as those encountered in the sea-of-gate layout.>

The authors present a rip-up-and-rerouter based on a matrix representation scheme and simulated evolution technique for solving detailed routing problems in VLSI layout. The status of the routing region is represented as a matrix. Rip-up and reroute operations are emulated as matrix subtractions and additions, respectively. The quality of a routing result can be measured by a few simple matrix operations on the matrix. A rip-up and reroute switch-box/channel router, called SILK, using a simulated evolution technique has been implemented based on this representation alone. Experimental results showed that SILK, when solving all the benchmarks from the literature, outperformed WEAVER, the most successful switch-box router to date, in both quality and speed aspects.>

A representation scheme for a rip-up and rerouter is presented. The status of the routing region is represented as a four-dimensional matrix. Rip-up and re-route operations are emulated as matrix subtractions and additions, respectively. The quality of a routing result can be measured by performing a few simple matrix operations. A rip-up and reroute switch-box/channel router called SILK, using a simulated evolution technique, has been implemented on the basis of this representation scheme. Experimental results showed that SILK outperformed WEAVER, the most successful switch-box router to date, in both quality and speed aspects, for all the classical benchmarks available.>