Blood glucose level (BGL) prediction contributes to more effective management of diabetes. Physical activity (PA), which affects BGL, is a crucial factor in diabetes management. Due to the erratic nature of PA's impact on BGL inter- and intra-patients, deploying PA in BGL prediction is challenging. Hence, it is crucial to discover optimal approaches for utilising PA to improve the performance of BGL prediction. This work contributes to this gap by proposing several PA-informed BGL prediction models. Different approaches are developed to extract information from PA data and integrate this information with BGL data at signal, feature, and decision levels. For signal-level fusion, different automatically-recorded PA data are fused with BGL data. Also, three feature engineering approaches are developed for feature-level fusion: subjective assessments of PA, objective assessments of PA, and statistics of PA. Furthermore, in decision-level fusion, ensemble learning is used to combine predictions from models trained with different inputs. Then, a comparative investigation is performed between the developed PA-informed approaches and the no-fusion approach, as well as between themselves. The analyses are performed on the publicly available Ohio dataset with rigorous evaluation. The results show that among the developed approaches, fusing heart rate data at the signal-level and PA intensity categories at the feature-level with BGL data are effective ways of deploying PA in BGL prediction.

NIST has selected CRYSTALS-Kyber as the primary Key Encapsulation Mechanism (KEM) algorithm for the standardization process of post-quantum cryptography. This paper proposes a high-speed hardware accelerator targeting the polynomial multiplication of Kyber. The NTT-based algorithm is employed in Kyber to perform polynomial multiplication, where modular multiplication is the most time-consuming operation in the computation of the NTT. This paper proposes a new Residue Number System (RNS) methodology to perform the modular multiplication in Kyber based on fast look-up tables with a novel sub-moduli RNS decomposition of the operation into smaller tables. A high-speed polynomial multiplier FPGA accelerator is developed based on the proposed RNS modular multiplier for both single and double butterfly modes. The resulting designs were implemented on Xilinx Artix-7 FPGA, and post-place and route hardware results obtained confirmed the significant improvements over state-of-art.

Optimal and sustainable control of blood glucose levels (BGLs) is the aim of type-1 diabetes management. The automated prediction of BGL using machine learning (ML) algorithms is considered as a promising tool that can support this aim. In this context, this paper proposes new advanced ML architectures to predict BGL leveraging deep learning and ensemble learning. The deep-ensemble models are developed with novel meta-learning approaches, where the feasibility of changing the dimension of a univariate time series forecasting task is investigated. The models are evaluated regression-wise and clinical-wise. The performance of the proposed ensemble models are compared with benchmark non-ensemble models. The results show the superior performance of the developed ensemble models over developed non-ensemble benchmark models and also show the efficacy of the proposed meta-learning approaches.

In type 1 diabetes, diurnal activity routines are influential factors in insulin dose calculations. Bolus advisors have been developed to more accurately suggest doses of meal-related insulin based on carbohydrate intake, according to pre-set insulin to carbohydrate levels and insulin sensitivity factors. These parameters can be varied according to the time of day and their optimal setting relies on identifying the daily time periods of routines accurately. The main issues with reporting and adjustments of daily activity routines are the reliance on self-reporting which is prone to inaccuracy and within bolus calculators, the keeping of default settings for daily time periods, such as within insulin pumps, glucose meters, and mobile applications. Moreover, daily routines are subject to change over periods of time which could go unnoticed. Hence, forgetting to change the daily time periods in the bolus calculator could contribute to sub-optimal self-management. In this paper, these issues are addressed by proposing a data-driven model for identification of diabetes diurnal patterns based on self-monitoring data. The model uses time-series clustering to achieve a meaningful separation of the patterns which is then used to identify the daily time periods and to advise of any time changes required. Further improvements in bolus advisor settings are proposed to include week/weekend or even modifiable daily time settings. The proposed model provides a quick, granular, more accurate, and personalized daily time setting profile while providing a more contextual perspective to glycemic pattern identification to both patients and clinicians.

[Formula: see text] is a primary marker of long-term average blood glucose, which is an essential measure of successful control in type 1 diabetes. Previous studies have shown that [Formula: see text] estimates can be obtained from 5-12 weeks of daily blood glucose measurements. However, these methods suffer from accuracy limitations when applied to incomplete data with missing periods of measurements. The aim of this article is to overcome these limitations improving the accuracy and robustness of [Formula: see text] prediction from time series of blood glucose. A novel data-driven [Formula: see text] prediction model based on deep learning and convolutional neural networks is presented. The model focuses on the extraction of behavioral patterns from sequences of self-monitored blood glucose readings on various temporal scales. Assuming that subjects who share behavioral patterns have also similar capabilities for diabetes control and resulting [Formula: see text], it becomes possible to infer the [Formula: see text] of subjects with incomplete data from multiple observations of similar behaviors. Trained and validated on a dataset, containing 1543 real world observation epochs from 759 subjects, the model has achieved the mean absolute error of 4.80 [Formula: see text] mmol/mol, median absolute error of 3.81 [Formula: see text] mmol/mol and [Formula: see text] of 0.71 ± 0.09 on average during the 10 fold cross validation. Automatic behavioral characterization via extraction of sequential features by the proposed convolutional neural network structure has significantly improved the accuracy of [Formula: see text] prediction compared to the existing methods.

In this paper, a new approach, based on the generalized triangular decomposition (GTD), is proposed for simultaneous wireless information and power transfer (SWIPT) in the spatial domain for a point-to-point multiple-input-multiple-output (MIMO) system. The approach exploits the structure of the GTD to allow the transmitter to use each of the strongest subchannels jointly for energy harvesting and information exchange while the receiver has the ability to harvest energy or decode information from each different received subchannel. An optimal solution is developed in the paper for SWIPT based on GTD that jointly obtains the optimal subchannels assignment and minimizes the total transmitted power for given information rate and energy harvesting constraints under a limited available power per each subchannel at the transmitter. Both the theoretical and numerical results presented in this paper show that our proposed approach significantly outperforms the state of the art spatial domain SWIPT systems based on the singular value decomposition (SVD).

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).

In this paper, we propose a novel parallel Elliptic-Curve-Cryptography (ECC) point multiplication implementation over binary Galois Field, GF(2m) by exploiting the advantage of concurrent operation in a homogeneous multi-core processor to yield an improved performance. A modified Lopez-Dahab (LD) mix-coordinates point multiplication algorithm is developed that exploits concurrency and enables operation using parallel instructions. The algorithm is used to implement ECC point multiplication over GF(2^163) on an Xmos multi-core microcontroller. The results obtained show a 60% performance improvement can be achieved over a single core implementation. Our presented implementation is believed to be the first parallel implementation of ECC scalar point multiplication over binary fields on a homogeneous multi-core microcontroller.

High speed Elliptic Curve Cryptography (ECC) implementations on Field Programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication (PM). In this paper, we present a combined Montgomery point multiplication algorithm to achieve low latency ECC point multiplication by using novel pipelined full precision parallel multipliers over GF(2m). We adopt a careful schedule of point operations to achieve low latency and a smart pipelining in the ECC architecture to reduce the critical path delay. Our proposed ECC architecture is implemented on Virtex5 (XCV5LX110) for a fair comparison and on Virtex7 (XC7VX550T) to quantify performance. Our Virtex5 based implementation over GF(2163), consumes 10363 slices, takes only 5.1 μs for an ECC point multiplication with a frequency of 153 MHz, and has a latency of 780 clock cycles. Our Virtex-5 performance outperforms the fastest reported work on the same platform. Our Virtex7 implementation which can compute an ECC PM in 3.50 μs at a frequency of 223 MHz while utilising only 8736 slices is the highest speed implementation reported to date on FPGA.

A new FPGA design for the Advanced Encryption Standard (AES) is presented in this paper. This design is believed to be the smallest memory free FPGA implementation of the AES encryption only requiring 184 slices on a Xilinx Spartan 3 (XC3S50) device, and 80 slices on a Spartan 6 (XC6SLX4) device while achieving throughputs of 36.5Mbps and 58.13Mbps respectively. This FPGA design adopts an 8-bit architecture and exploits the specific fabric in Spartan 3 and Spartan 6 generation FPGAs to optimize the implementation of the shifting operations.

A new method using polynomial residue number systems (PRNS) is introduced in this paper to protect the Advanced Encryption Standard (AES) against faults attacks. By using PRNS, the byte based AES operations over GF(28) are decomposed into several parallel operations that use its residues over smaller fields. In this implementation, three GF(24) irreducible polynomials are selected as the moduli set for the chosen PRNS, including a redundant modulus to achieve error detection. Three GF(24) AES cores are constructed individually according to the chosen moduli. This PRNS architecture brings several advanced features to AES design from the scope of anti-side-channel analysis. Firstly, for each 8-bit GF(28) element, this implementation is capable of detecting up to 4 bit errors that occur in a single GF(24) AES core. Secondly, thanks to the data independency between PRNS operations, the distributed PRNS AES cores have an intrinsic resistance against probing attacks. In addition, due to the introduction of redundant information and the residue representation replacing the original representation, more confusion is added to the system, which may also enhance the design's security. To the authors' knowledge, this is the world's first PRNS AES implementation. Hardware implementation results are also given in this paper.

In this paper, we investigate the potential of the hardware/software co-design to realize a flexible-low resources elliptic curve cryptography (ECC) processor over binary finite fields GF(2m) on FPGA platforms. A design is proposed that is capable to work over different curves recommended by the ECC standards, namely, m = 163, 283, 571 without reconfiguring either the software or the hardware. The proposed hardware-software co-design is hosted on a free-so ft-core processor from Xilinx FPGA, namely the PicoBlaze. Two novel arithmetic circuits that represent the hardware environment are introduced to perform multi-precision arithmetic and scalable reduction over GF(2m). Furthermore, the proposed architecture is parameterized for different data widths (8, 16, 32 bits) to evaluate the optimal resource utilization versus performance trade-off to be made for the low resource-end application while still maintaining flexibility (scalability) across the chosen curves. The implementation of the flexible ECC processor consumes only 392 (51%) and 534 (62%) slices of the lowest cost chips from Xilinx Spartan III namely XC3S50 for 8 and 16-bits data paths, and 1278 (66%) slices for 32-bit data path on Spartan III XC3S200.

A scalable block cipher based on a filter bank structure over GF(28) is proposed. The filter bank structure is used to introduce the diffusion during the circular convolution process between the filters coefficients (which are generated from the key) and the plaintext. The confusion is achieved by the mixing between the analysis filter bank and a novel addition mod 2nand XOR scheme. The proposed cipher is scalable in both block and key lengths. The cipher is shown to be secure against differential and linear cryptanalysis and of lesser complexity than the AES. The proposed cipher structure enables security versus complexity versus performance trade-offs to be made, an increasingly important aspect of security in communications systems.

In this work, two new low area designs on FPGA for a scalable elliptic curve point multiplication are presented. The first design is a pure software implementation on a compact 8-bit embedded microcontroller, the PicoBlaze from Xilinx. The second is a novel hardware architecture for a compact ECC processor. Both designs are scalable across the curves m=113,131,163,193 recommended by SECG and consume respectively only (23%) and (61%) of the available resources on the smallest and lowest cost Spartan-III XC3S50 device. The proposed designs are believed to be the first smallest reported designs to date that support scalability with low area for a suite of curves recommended by an ECC standard.

In this paper, we investigate the potential of a hardware/software co-design methodology to realize a low resources scalable elliptic curve cryptography (ECC) processor over binary finite fields GF(2m) on an FPGA platform. The software is hosted on a free-soft-core processor from Xilinx FPGA (PicoBlaze); while two novel arithmetic circuits serve as the hardware environment to perform multi-precision arithmetic and scalable reduction. The proposed design is capable to work over a suite of curves recommended by NIST, namely, m= 163, 233, 283, 409, 571 without reconfiguring either the software or hardware. The proposed architecture is parameterized for data widths 8, 16, 32 bit to evaluate performance versus area trade-offs. The implementation of the scalable ECC processor consumes only 452 (58%) and 559 (72%) slices of the lowest cost chips from Xilinx Spartan III namely XC3S50 for 8 and 16-bits data paths, and 1127 (60%) slices for 32-bit data path on Spartan III XC3S200. Such design developed on FPGA is ideal for System-on-Chip (SOC) integration or can operate as a standalone processor for low-resource applications requiring strong security.

This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-μm CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 μm2and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power-latency-area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.

A scalable block cipher based on a filter bank structure over GF(28) is proposed. The filter bank structure is used to introduce the diffusion during the circular convolution process between the filters coefficients (which are generated from the key) and the plaintext. The confusion is achieved by the mixing between the analysis filter bank and a novel lifting scheme. The proposed cipher is scalable in both block and key lengths. The cipher is shown to be secure against differential and linear cryptanalysis and of comparable complexity to the AES.

This paper presents a practical realization of a secure passive (battery-less) RFID tag. The tag consists of an off the shelf front end combined with a bespoke 0.18 mum ASIC assembled as a credit card sized prototype. The ASIC integrates the authors' ultra low power novel AES design together with a novel random number generator and a novel protocol which provides both security and privacy. The analysis presented shows a security of 64-bits against many attack methods. Both modeled and measured power results are presented. The measured average core power consumed during continuous normal operation is 1.36 muW.

This paper details the design of a new high-speed pipelined application-specific instruction set processor (ASIP) for elliptic curve cryptography (ECC) using field-programmable gate-array (FPGA) technology. Different levels of pipelining were applied to the data path to explore the resulting performances and find an optimal pipeline depth. Three complex instructions were used to reduce the latency by reducing the overall number of instructions, and a new combined algorithm was developed to perform point doubling and point addition using the application specific instructions. An implementation for the United States Government National Institute of Standards and Technology-recommended curve over GF(2163) is shown, which achieves a point multiplication time of 33.05 s at 91 MHz on a Xilinx Virtex-E FPGA-the fastest figure reported in the literature to date. Using the more modern Xilinx Virtex-4 technology, a point multiplication time of 19.55 s was achieved, which translates to over 51120 point multiplications per second.

Two designs have been presented for high throughput pipelined implementation using field-programmable gate arrays (FPGAs) of the advanced encryption standard (AES). Both are believed to be faster than the existing FPGA designs and achieve throughputs of 30 and 28 Gbps. The fastest design achieves a throughput, for either encipher or decipher, in excess of 30 Gbps using a Xilinx Spartan-III part and allows key changes every 120 cycles. A second design achieves a throughput of 28 Gbps using a Xilinx Virtex-II part and supports both key and encipher/decipher changes every clock cycle. In order to achieve this, careful floor planning and a novel pipelined key expander were developed together with modifications to the MixColumns and composite field implementation of the SubBytes operation. Such an architecture has application for servers supporting multiple AES secure channels and can support, in a multi-channel environment, any feedback mode, including cipher block chaining. Previous pipelined designs have not shown this capability.

Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2n-(2n-2+1) addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130 mm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space

Novel modulo 2n-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area × delay2and energy × delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology.

This paper presents a very low area design for the advanced encryption standard (AES) capable of functioning in three of its feedback modes to provide flexible support for its use as a stream cipher. The architecture is based around an 8-bit application specific instruction processor (ASIP) and includes UARTs to support asynchronous serial I/O. The entire design fits within the smallest Xilinx Spartan-II FPGA (XC2S15), occupying 174 slices and two block memories. The design achieves a throughput of 2.3 Mbps with a 70MHz clock in OFB, CTR and CFB modes. The size is approximately 27% smaller than a comparable RC4 design

The design of flexible elliptic curve cryptography processors (ECP) is considered in this paper. Novel word-level algorithms and implementations for the underlying GF(2/sup m/) multiplication and squaring arithmetic which enable improved flexibility versus performance tradeoffs, are presented and employed in the design of an efficient flexible ECP architecture; corresponding field-programmable gate-array (FPGA) prototyping results for two different processor word lengths are also included for evaluation.

A novel reconfigurable Viterbi decoder is proposed, based on an area-efficient ACS architecture, in which the constraint length and traceback depth can be on-line reconfigurable to trade-off decoding capability and decoding speed. Key techniques of the decoder are 5-level ACS (add-compare-select) pipelining and in-place path metric updating, which result in very high decoding speed and low memory usage. To verify the performance of the decoder, an example design with constraint length 7 to 10, has been successfully implemented on Xilinx Virtex FPGA devices. FPGA implementation results, in terms of decoding speed, resource usages and BER, have been obtained. These confirmed the functionality and the expected higher speeds and lower resources.

Generalized minimum distance (GMD) decoding is a variant of soft-decision decoding for RS codes. It is well known that soft-decision decoding gives around 2 dB more coding gain than the conventional hard-decision decoding. However, most research has concentrated on soft-decision-decoding for convolutional codes. In this paper, we present the implementation of GMD decoding for RS codes using a modified Welch-Berlekamp Algorithm. A pilot design RS(31, 27) GMD decoder has been successfully implemented on a XILINX FPGA.

This paper deals with the hardware implementation of soft decision decoding (SDD) of Reed-Solomon (RS) codes. An efficient algorithm for hardware implementation of generalized minimum distance (GMD) decoding of RS codes is presented and employed in the design of a pilot RS(63,42) codec on FPGAs.

N-digit, radix-α bases are proposed for VLSI implementation of redundant arithmetic, mod m, wherem= ±1,m≠±1, for 0 < j < N and m is prime. These bases simplify arithmetic overflow and are well suited to redundant arithmetic. The representations provide competitive, multiplierless T-point number theoretic transforms, mod m, where Tl N or Tl 2N.

In this paper an algorithm for GF(2/sup m/) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different GF(2/sup m/) and hence suitable for VLSI implementations. As in the bit-serial case these bit-parallel multipliers can also be hardwired to carry out constant multiplication. These constant multipliers have reduced hardware requirements and are also simple to design. In addition, the multiplication/division algorithm also allows a bit-serial systolic finite field divider to be designed. This divider is modular, independent of the defining irreducible polynomial for the field, easily expanded to different GF(2/sup m/) and its longest delay path is independent of m.

In this transaction brief we consider the design of dual basis inversion circuits for GF(2/sup m/). Two architectures are presented-one bit-serial and one bit-parallel-both of which are based on Fermat's theorem. Finite field inverters based on Fermat's theorem have previously been presented which operate over the normal basis and the polynomial basis. However there are two advantages to be gained by forcing inversion circuits to operate over the dual basis. First, these inversion circuits can be utilized in circuits using hardware efficient dual basis multipliers without any extra basis converters. And second, the inversion circuits themselves can take advantage of dual basis multipliers, thus reducing their own hardware levels. As both these approaches require squaring in a finite field to take place, a theorem is presented which allows circuits to be easily designed to carry out squaring over the dual basis.

A bit-serial dual basis systolic multiplier for GF(2/sup m/) is presented. In addition to carrying out bit-serial, 2-variable input multiplication, the presented multiplier can also carry out constant multiplication and if one of the inputs is entered in bit-parallel form, the hardware requirements of the multiplier can be reduced still further. The proposed multiplier is suitable for use in high speed Reed-Solomon decoders such as in inverse transform circuits and recursive extension circuits. This multiplier is an improved and extended version of a bit-serial systolic multiplier previously presented by the authors.

A bit-serial systolic divider for GF(2/sup m/) is presented. By virtue of being systolic this divider is modular, nearest neighbour connected and the longest delay path is independent of m and consequently it is well suited to VLSI implementation. Furthermore it is shown that this divider displays a number of advantages over a similar systolic divider, the foremost of which is that it operates over the dual basis. Circuits using this divider can therefore utilise other hardware efficient dual basis operators such as the Berlekamp multiplier.>

This paper proposes a fault-tolerant linear convolution architecture using Residue Number Systems (RNS) and Polynomial Residue Number Systems (PRNS). The RNS and PRNS are both given error-detection capability by the addition of redundant residue channels, and the combined redundancy enables error-correction without explicit error-decoding. The method is simple, fast, and amenable to VLSI implementation.>