Demo Data from EDBT 2026 / reviewers in the wild / expert
Zion Cien Shen
dblp:98/4615
· DBLP profile ↗
7ranked-venue papers
3as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% | |
| Theoretical computer science
1 paper |
Combinatorics and discrete mathematics · 50% Coding theory · 50% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.1 | 3 | 2005 | An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 Twin binary sequences: a nonredundant representation for general nonslicing floorplan · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 Bounds on the number of slicing, mosaic, and general floorplans · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › physical design
floorplanning |
0.1 | 2 | 2003 | Twin binary sequences: a nonredundant representation for general nonslicing floorplan · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 Bounds on the number of slicing, mosaic, and general floorplans · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › physical design › interconnect optimization
buffer insertion and wire sizing |
0.1 | 1 | 2005 | An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 |
Electronic design automation › physical design › routing
routing tree construction |
0.1 | 1 | 2005 | An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 |
Coding theory › error-correcting codes › coding bounds
asymptotic bounds |
0.0 | 1 | 2003 | Bounds on the number of slicing, mosaic, and general floorplans · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Combinatorics and discrete mathematics
enumeration |
0.0 | 1 | 2003 | Bounds on the number of slicing, mosaic, and general floorplans · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation › physical design › routing
timing-driven routing |
0.0 | 1 | 2005 | An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 |
Methods — techniques the papers use, named apart from their topics
combinatorial enumeration · 0.1asymptotic analysis · 0.1stochastic search · 0.1lookup table · 0.1twin binary sequences · 0.0mosaic floorplan · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | Efficient Rectilinear Steiner Tree Construction with Rectilinear BlockagesabstractGiven n points on a plane, a rectilinear Steiner minimal tree (RSMT) connects these points through some extra points called Steiner points to achieve a tree with minimal total wire length. Taking blockages into account dramatically increases the problem complexity. It is extremely unlikely that an efficient optimal algorithm exists for rectilinear Steiner minimal tree construction with rectilinear blockages (RSMTRB). Although there exist some heuristic algorithms for this problem, they have either poor quality or expensive running time. In this paper, we propose an efficient and effective approach to solve RSMTRB. The connection graph we used in this approach is called spanning graph which only contains O(n) edges and vertices. An O(n log n) time algorithm is proposed to construct spanning graph for RSMTRB. The experimental results show that this approach can achieve a solution with significantly reduced wire length. The total run time increased is negligible in the whole design flow. Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li |
ICCD | 1 |
| 2005 | An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerationsabstractIn this paper, we propose a fast algorithm to construct a performance-driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently, several algorithms have been published addressing the routing tree construction problem. However, all these algorithms are slow and not scalable. In this paper, we propose an algorithm which is fast and scalable with problem size. The main idea of our approach is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features, the size of stochastic search space is small and can be searched in very little time. The solutions for the components are either pre-generated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since it is efficient to obtain solutions for components, it is also efficient to construct and evaluate the whole routing tree for each specification. Experimental results show that, for trees of moderate size, our algorithm out performs the previous algorithms in both quality and runtime. Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2004 | An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations
Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
ASP-DAC | 2 |
| 2004 | Accurate and efficient flow based congestion estimation in floorplanning
Zion Cien Shen, Chris C. N. Chu |
ASP-DAC | 1 |
| 2003 | Bounds on the number of slicing, mosaic, and general floorplansabstractA floorplan can be defined as a rectangular dissection of the floorplan region. Simple and tight asymptotic bounds on the number of floorplans for different dissection structures help us to evaluate the size of the solution space of different floorplan representation. They are also interesting theoretically. However, only loose bounds exist in the literature. In this paper, we derive tighter asymptotic bounds on the number of slicing, mosaic and general floorplans. Consider the floorplanning of n blocks. For slicing floorplan, we prove that the exact number is n!((-1)/sup n+1//2)/spl Sigma//sub k=0//sup n/(3+/spl radic/8)/sup n-2k/(/sub k//sup 1/2/)(/sub n - k//sup 1/2/) and the tight bound is /spl Theta/(n!2/sup 2.543n//n/sup 1.5/) [9] . For mosaic floorplan, we prove that the tight bound is /spl Theta/(n!2/sup 3n//n/sup 4/). For general floorplan, we prove a tighter lower bound of /spl Omega/(n!2/sup 3n//n/sup 4/) and a tighter upper bound of O(n!2/sup 5n//n/sup 4.5/). Zion Cien Shen, Chris C. N. Chu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2003 | Twin binary sequences: a nonredundant representation for general nonslicing floorplanabstractThe efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Nonslicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and nonredundant topological representation for nonslicing structure. In this paper, we propose the first representation of this kind. Like some previous work (Zhou et al. 2001), we have also made use of a mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules (that will increase the size of the solution space significantly), our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan such that every nonslicing floorplan can be obtained uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!2/sup 3n//n/sup 1.5/), which is the size without empty room insertion, but every nonslicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2002 | Twin binary sequences: a non-redundant representation for general non-slicing floorplanabstractThe efficiency and effectiveness of many floorplanning methods depend very much on the representation of the geometrical relationship between the modules. A good representation can shorten the searching process so that more accurate estimations on area and interconnect costs can be performed. Non-slicing floorplan is the most general kind of floorplan that is commonly used. Unfortunately, there is not yet any complete and non-redundant topological representation for non-slicing structure. In this paper, we will propose the first representation of this kind. Like some previous work [9], we have also made used of mosaic floorplan as an intermediate step. However, instead of including a more than sufficient number of extra dummy blocks in the set of modules, our representation allows us to insert an exact number of irreducible empty rooms to a mosaic floorplan in such a way that every non-slicing floorplan can be obtained by this method uniquely from one and only one mosaic floorplan. The size of the solution space is only O(n!23n/n1.5) but every non-slicing floorplan can be generated uniquely and efficiently in linear time without any redundant representation. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
ISPD | 3 |