EDBT 2026 Demo / reviewers in the wild / expert
Shou-Chung Yang
dblp:98/4885
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 28% Processor architecture and microarchitecture · 28% Memory systems · 28% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 1 | 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY Memories · IEEE Trans. Computers 1975 |
Processor architecture and microarchitecture
microprogramming |
0.0 | 1 | 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY Memories · IEEE Trans. Computers 1975 |
Memory systems › non-volatile memory
read-only memory |
0.0 | 1 | 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY Memories · IEEE Trans. Computers 1975 |
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY Memories · IEEE Trans. Computers 1975 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY Memories · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
single-transition time state assignment · 0.0self-clocked mode · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | Design of Asynchronous Sequential Networks Using READ-ONLY MemoriesabstractThe application of microprogrammed READ-ONLY memories in the design of asynchronous sequential networks is investigated. Variations of single-transition time (STT) state assignments are shown to be applicable to the problem of assigning memory addresses to a memory representation of an asynchronous network. Design algorithms are developed which allow the implementation of an asynchronous sequential network as a READ-ONLY memory. Two operating modes are considered: normal asynchronous operation and a self-clocked mode in which sequential outputs are allowed on a single-input change, thus providing a means of implementing functions normally achieved with synchronous (clocked) networks. In addition the practical timing constraints of the proposed methods are considered. Howard A. Sholl, Shou-Chung Yang |
IEEE Trans. Computers | 2 |