A high input impedance read-out integrated circuit (IC) for DC measurements has been implemented. The proposed read-out IC consists of a capacitively coupled instrumentation amplifier (CCIA) and an incremental delta-sigma ($\Delta \Sigma )$analog-to-digital converter (ADC). An impedance boosting technique, combining the conventional positive-feedback loop with a proposed fine current compensation loop (FCCL), is introduced to enhance the input impedance of the CCIA. Additionally, the proposed structure chops the entire signal chain at a global chopping frequency of 13.2 kHz, which is higher than the 1/$f$corner frequency of the CCIA’s main amplifier. This approach further increases the input impedance of the CCIA and eliminates the need for RRL and an analog low pass filter (LPF), thereby reducing circuit complexity and area. Local auto-zeroing and correlated double sampling techniques are also used to suppress the offset and 1/$f$noise of the read-out IC. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) digital filter. Implemented in a 0.13$\mu $m CMOS process, the prototype chip occupies an area of 3.808 mm$^{2}$and draws 1.32 mA from a 5 V supply. The input impedance is boosted from 4.4 M$\Omega $to 5.1 G$\Omega $, corresponding to an impedance boosting factor of 1153. The measurement results show an input-referred noise of 2.4$\mu $V$_{\mathrm{RMS}}$with a conversion time of 0.076 ms. The input range of the ROIC is 4.8 V and it achieves the Schreier figure of merit of 164.9 dB.

Neural Radiance Field (NeRF) has broken new ground in the novel view synthesis due to its simple concept and state-of-the-art quality. However, it suffers from severe performance degradation unless trained with a dense set of images with different camera poses, which hinders its practical applications. Although previous methods addressing this problem achieved promising results, they relied heavily on the additional training resources, which goes against the philosophy of sparse-input novel-view synthesis pursuing the training efficiency. In this work, we propose MixNeRF, an effective training strategy for novel view synthesis from sparse inputs by modeling a ray with a mixture density model. Our MixNeRF estimates the joint distribution of RGB colors along the ray samples by modeling it with mixture of distributions. We also propose a new task of ray depth estimation as a useful training objective, which is highly correlated with 3D scene geometry. Moreover, we remodel the colors with regenerated blending weights based on the estimated ray depth and further improves the robustness for colors and viewpoints. Our MixNeRF outperforms other state-of-the-art methods in various standard benchmarks with superior efficiency of training and inference.

Video frame interpolation is the task of creating an interframe between two adjacent frames along the time axis. So, instead of simply averaging two adjacent frames to create an intermediate image, this operation should maintain semantic continuity with the adjacent frames. Most conventional methods use optical flow, and various tools such as occlusion handling and object smoothing are indispensable. Since the use of these various tools leads to complex problems, we tried to tackle the video interframe generation problem without using problematic optical flow. To enable this, we have tried to use a deep neural network with an invertible structure, and developed an U-Net based Generative Flow which is a modified normalizing flow. In addition, we propose a learning method with a new consistency loss in the latent space to maintain semantic temporal consistency between frames. The resolution of the generated image is guaranteed to be identical to that of the original images by using an invertible network. Furthermore, as it is not a random image like the ones by generative models, our network guarantees stable outputs without flicker. Through experiments, we confirmed the feasibility of the proposed algorithm and would like to suggest the U-Net based Generative Flow as a new possibility for baseline in video frame interpolation. This paper is meaningful in that it is the new attempt to use invertible networks instead of optical flows for video interpolation.

When online learners have questions that are related to a specific task, they often use Q&A boards instead of web search because they are looking for context-specific answers. While lecturers, teaching assistants, and other learners can provide context-specific answers on the Q&A boards, there is often a high response latency which can impede their learning. We present automaTA, a prototype that suggests context-specific answers to online learners' questions by capturing the context of the questions. Our solution is to automate the response generation with a human-machine mixed approach, where humans generate high-quality answers, and the human-generated responses are used to train an automated algorithm to provide context-specific answers. automaTA adopts this approach as a prototype in which it generates automated answers for function-related questions in an online programming course. We conduct two user studies with undergraduate and graduate students with little or no experience with Python and found the potential that automaTA can automatically provide answers to context-specific questions without a human instructor, at scale.

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a ¿response feature¿ detector and ¿hardware tuning knobs,¿ designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, post-manufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test ¿truly self-healing¿ systems in the near future.

Frequency modulation is used in many important communication and wireless applications. A key defining characteristic of frequency modulated systems is the constant amplitude of the transmitted signal making it impossible to use envelope-based built-in test (BIT) techniques. In this paper, an efficient BIT technique for such transmitters using lowpass filters is proposed. The proposed BIT technique is low-cost and has minimal impact on RF transmitter performance. It can also be used to efficiently test devices such as voltage-controlled oscillators (VCOs), phase locked loops (PLL) etc through frequency discrimination. Simulation results and hardware measurements demonstrate the feasibility of the proposed approach.

This paper presents a hardware jitter expansion technique to enable high-resolution jitter measurement of multi-GHz digital signals. To realize high-resolution timing analysis, the jitter is reconstructed on a low-speed signal and jitter measurements are made on this signal instead of the original high-speed signal. The reconstructed jitter on the low-speed signal occurs on a proportionately larger time-scale as opposed to the original jitter on the high-speed signal. Consequently, the jitter on the low-speed signal can be measured easily using conventional jitter measurement techniques and mapped back to its corresponding value relative to the high-speed signal. The approach allows one or two orders of magnitude smaller jitter values to be measured than standard jitter measurement techniques available today. The proposed hardware is easily implemented as a front-end to any existing jitter measurement system. Simulation data and hardware measurements are presented to prove the viability of the proposed scheme.

Due to aggressive technology scaling, parametric failure diagnosis of RF transceiver modules is becoming important for rapid yield ramp-up. In this paper, a low cost diagnosis approach is proposed that is amenable to built-in diagnosis of RF transceivers via diagnostic algorithms running on the transceiver DSP. The method relies on the use of a single sensor at the transmitter output that eliminates the need to make costly RF measurements. In addition, module level diagnosis is possible without the need for probing other internal RF signals. A sequence of specially crafted stimuli, are applied to the transceiver from the on-board DSP processor. The sensor and received baseband output signals are analyzed and the specifications of embedded RF modules are extracted from the test response data. The proposed approach is demonstrated using simulation and hardware measurements on a 2.45GHz transceiver. Experiment results show high diagnosis accuracy of parametric failures in embedded RF modules.

To address growing production test costs, a low-cost built-in test solution for RF circuits is proposed that is robust to Process, Supply Voltage and Temperature variations (PVT variations). The test solution consists of measuring the envelope of the output response to a twotone test stimulus. This is a relatively low frequency signal compared to the nominal frequency of the RF device under test (DUT) and can therefore be sampled using an on-chip ADC. The resulting test response waveform is analyzed using wavelet transforms. The corresponding wavelet coefficients are used to accurately predict the test specification values of the RF DUT in the presence of noise. The proposed test approach has been demonstrated for a 2.4GHz low noise amplifier designed in a 0.18um CMOS process and shows high prediction accuracy for the test specifications of the DUT in the presence of noise and PVT variations.

In the nanometer design regime, analog and RF circuits are expected to be increasingly susceptible to process, noise and thermal variations. Shifting threshold voltages on the NMOS and PMOS devices of a mixer, LNA or power amplifier, for example, can affect the design specifications of such circuits (such as gain). Thermal variations can affect carrier mobilities of NMOS and PMOS devices differently, further affecting circuit performance. To solve these problems, a new self-calibration approach driven by a Specification-driven built-in self test procedure (S-BIST) is proposed. This S-BIST procedure uses alternate specification test techniques to predict the performance specifications of the circuit-under-test from the S-BIST response. The results of the S-BIST procedure are used to change the operating point of the circuit to maximally compensate the analog/RF circuit for loss of performance. The proposed S-BIST approach has been applied to a 2.4-GHz low noise amplifier and performs well in the presence of temperature and process variations.

In this paper a cost metric has been proposed, which can drive device resizing during circuit design with the objective of efficient low-cost production test of analog circuits. A test cost reduction method using dynamic and selective elimination of specification tests for fault-free circuits has also been proposed. The test elimination method exploits correlations between analog specifications. Higher correlation allows one specification to be tested (without performing measurements) against its acceptability limits by analyzing measurement data corresponding to the other correlated specification. The proposed cost metric can be imported into any typical device-resizing algorithm used in analog synthesis tools, which try to optimize circuit performance and manufacturing yield. Simulation results using op-amps show the feasibility and the effectiveness of the proposed cost metric.