Spatially distributed 3D circuit models are extracted with a segment-to-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather than using the traditional net-to-net approach. Critical issues regarding the extraction efficiency and accuracy of segment-to-segment BEM capacitance models are explored. An adaptive discretization scheme is developed for segment-to-segment capacitance extraction and also applied to segment-to-segment high-frequency inverse inductance extraction. We demonstrate the limitations of the duality between capacitance and inverse inductance. Examples demonstrating the accuracy of these models are presented for real packaging cases.

Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today's integrated systems, however, makes fast analysis crucial as well. We present a novel hierarchical potential evaluation technique which is able to represent detailed near-field and global far-field couplings with equal accuracy and efficiency by combining the best features of known hierarchical approaches in this field.

Full three-dimensional (3D) inductance models of on-chip interconnect contain an extremely large number of forward coupling terms. It is therefore desirable to use a two-dimensional (2D) approximation in which forward couplings are not included. Unlike capacitive coupling, however, truncating mutual inductance terms can result in loss of accuracy and even instability. This paper investigates whether ignoring forward couplings is an acceptable choice for all good IC designs or if full 3D models are necessary in certain on-chip interconnect configurations. We show that the significance of the forward coupling inductance depends on various aspects of the design.

Full 3D lumped partial inductance models usually contain a tremendous amount of forward coupling terms. To reduce the complexity of simulation and analysis, a simplified model that excludes the forward coupling terms is often adopted in practice. This paper addresses the question whether ignoring forward couplings is always an acceptable choice or if full 3D models are necessary in certain cases. We show that the significance of the forward coupling inductance depends on various aspects of the design.

Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of the magnetic couplings for final design verification can be a daunting task. In general, when modeling inductance and the associated return paths, one must consider the on-chip conductors as well as the system packaging. This can result in an RLC circuit size that is impractical for traditional simulators. In this paper we demonstrate a localized, window-based extraction and simulation methodology that employs the recently proposed susceptance (the inverse of inductance matrix) concept. We provide a qualitative explanation for the efficacy of this approach, and demonstrate how it facilitates pre-manufacturing simulations that would otherwise be intractable. A critical aspect of this simulation efficiency is owed to a susceptance-based circuit formation that we prove to be symmetric positive definite. This property, along with the sparsity of the susceptance matrix, enables the use of some advanced sparse matrix solvers. lye demonstrate this extraction and simulation methodology on some industrial examples.

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as skin and proximity effect. We also discuss and contrast options for stable and accurate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to consider the possibilities for pattern-matching style solutions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for inte-grated circuit design in recent years. This tutorial paper de-scribes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency ef-fects such as skin and proximity effect.

As advances in IC technologies and operating frequencies make the modeling of on--chip magnetic interactions a necessity, it is apparent that extension of traditional inductance extraction approaches to full-chip scale problems is impractical. There are primarily two obstacles to performing inductance extraction with the same efficacy as full-chip capacitance extraction: 1) neglecting far-away coupling terms can generate an unstable inductance matrix approximation; and 2) the penetrating nature of inductance makes localized extraction via windowing extremely difficult. In this paper we propose and contrast three new options for stable and accurate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to consider the possibilities for pattern-matching style solutions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.

We propose a new, efficient and accurate localized inductance modeling technique via windowing in a manner that is analogous to localized capacitance extraction. The stability and accuracy of this process is made possible by twice inverting the localized inductance models, and in the process exploiting properties of the magnetostatic interactions as modeled via the susceptance (inverse inductance). Application of these localized double-inverse inductance models to actual IC bus examples demonstrates the significant improvement in simulation efficiency and overall accuracy as compared to alternative methods of approximation and simplification.

To make three-dimensional (3-D) on-chip interconnect inductance extraction tractable, it is necessary to ignore parasitic couplings without compromising critical properties of the interconnect system. It is demonstrated that simply discarding faraway mutual inductance couplings can lead to an unstable approximate inductance matrix. In this paper, we describe an equipotential shell methodology, which generates a partial inductance matrix that is sparse yet stable and symmetric. We prove the positive definiteness of the resulting approximate inductance matrix when the equipotential shells are properly defined. Importantly, the equipotential shell approach also provably preserves the inductance of loops if they are enclosed entirely within the shells of their segments. Methods for sizing the shells to control the accuracy are presented. To demonstrate the overall efficacy for on-chip extraction, ellipsoid shells, which are a special case of the general equipotential shell approach, are presented and demonstrated for both on-chip and system-level extraction examples.

The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable proportions. Interconnect extraction tools employ hierarchy to manage complexity, but this hierarchy is discarded via eliminating far away coupling terms when the equivalent ARC circuits are Formed. The increasing dominance of capacitance coupling along with the emergence of on chip inductance, however, makes the composite effect of far-away couplings increasingly evident. Even if newly enforced design rules and practices will ultimately obviate the need for modeling these couplings for design verification, some approximation of the "exact" solution is required to validate these rules. This paper proposes an efficient hierarchical equivalent circuit representation of interconnect parasitics that utilizes the efficient hierarchical long-distance modeling already existing within extractors. Results from a prototype simulator based on these hierarchical models demonstrate the simulation inaccuracy incurred when the faraway coupling terms are ignored. Such a form of interconnect modeling may provide the key to hierarchical modeling of electro-magnetic interactions between large components on future gigascale systems.

Article IC analyses including extracted inductance models Share on Authors: Michael W. Beattie Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PA Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PAView Profile , Lawrence T. Pileggi Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PA Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 915–920https://doi.org/10.1145/309847.310098Online:01 June 1999Publication History 16citation337DownloadsMetricsTotal Citations16Total Downloads337Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings beyond the localized confines of functional design blocks. In addition, SOC design styles and gridless variable-width routing make it increasingly difficult to use precharacterized library shapes for parasitic extraction. A comprehensive capacitance and inductance extraction solution requires a hierarchical data representation and fast runtime algorithms. We illustrate through examples that both the multipole method and hierarchical refinement, which are the two most successful approaches for parasitic extraction to date, work efficiently only under certain, limiting conditions. To improve this situation we present an approach which combines the best of both methods into a concurrent multipole refinement representation of the electromagnetic interaction which is efficient for arbitrary interconnect configurations. We use a generalized formulation of electromagnetic interactions to exploit the similarities in capacitance and inductance extraction for greater efficiency.

The overwhelming size of the capacitance extraction problem forces designers to localize the capacitive coupling and determine a distance (a "window") outside of which the mutual capacitance between two wires is "small enough" to ignore. The primary difficulties with such approaches are determining how large the extraction windows have to be to capture all of the relevant mutual capacitances, and estimating the error incurred due to "windowing." This paper proposes solutions for both problems. We first show that the shift-truncate method and the windowing method yield opposite bounds for the exact values of the mutual and self capacitances. It is also shown that the capacitance matrices resulting from the application of these two localization methods are positive definite and, therefore, lead to stable approximations of the exact parasitics system. For the windowing method, we show that the original asymmetric capacitance matrix can be made symmetric while guaranteeing the positive definiteness and making the error bounds even tighter. In summary, we describe an adaptive window sizing methodology based on error values from the windowing and shift-truncate bounds. The proposed methodology is also potentially useful in identifying crosstalk problem zones for interconnect optimization and noise reduction, and for the generation of noise-reducing design rules.

In this paper we prove that simply discarding conductors beyonda certain spacing during BEM capacitance extraction willresult in a lower bound on the self-capacitance calculations andan upper bound on the mutual capacitance calculations that liewithin that spacing. We prove that a potential-shift and truncatescheme can yield bounds opposite to those for the truncate onlycase; namely, an upper bound on the self capacitance and a lowerbound on the mutual capacitance that lies within the chosenspacing. The ease with which the upper and lower bounds arecalculated is shown, and their utility for selection of an optimalwindow size is described. A metal shell is also presented here thatresults in bounds similar to those of shift-truncate. We furtherpropose a new potential-shift function that yields increased approximationaccuracy compared to shift-truncate in many cases.