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Arturo Cisneros

dblp:98/5476 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Optical networks · 50% Internet architecture and protocols · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 50% Hardware reliability and fault tolerance · 50%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › ATM networks
ATM switch architecture		 0.011991
A Large ATM Switch Based on Memory Switches and Optical Star Couplers · IEEE J. Sel. Areas Commun. 1991
Optical networks › optical switching
optical packet switching		 0.011991
A Large ATM Switch Based on Memory Switches and Optical Star Couplers · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
switching network		 0.011991
A Large ATM Switch Based on Memory Switches and Optical Star Couplers · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

memory switches · 0.0contention resolution · 0.0
YearPublicationVenuePosition
1991 A Large ATM Switch Based on Memory Switches and Optical Star Couplers
abstract
The authors propose a large asynchronous transfer mode (ATM) switch architecture based on memory switches of the type being developed by several research groups and on optical star couplers. Fast contention resolution makes it possible to combine a number of these modules, memory switches, and optical stars in order to attain a capacity of 2.5 Tb/s. This switch architecture has a relatively small failure group size of 128 STS-3 lines out of a total of 16384. The scaling of the switch to smaller capacities is discussed, showing how tradeoffs in the various parameters can be used to overcome particular technological limitations. Fault tolerance and recovery schemes are presented, showing that with minimal increase to the switch complexity and cost, a very reasonable fault recovery scheme is available for almost every sort of failure.>
Arturo Cisneros, Charles A. Brackett
 IEEE J. Sel. Areas Commun.1