In the current cloud business environment, the cloud provider (CP) can provide a means for offering the required quality of service (QoS) for multiple classes of clients. We consider the cloud market where various resources such as CPUs, memory, and storage in the form of Virtual Machine (VM) instances can be provisioned and then leased to clients with QoS guarantees. Unlike existing works, we propose a novel Service Level Agreement (SLA) framework for cloud computing, in which a price control parameter is used to meet QoS demands for all classes in the market. The framework uses reinforcement learning (RL) to derive a VM hiring policy that can adapt to changes in the system to guarantee the QoS for all client classes. These changes include: service cost, system capacity, and the demand for service. In exhibiting solutions, when the CP leases more VMs to a class of clients, the QoS is degraded for other classes due to an inadequate number of VMs. However, our approach integrates computing resources adaptation with service admission control based on the RL model. To the best of our knowledge, this study is the first attempt that facilitates this integration to enhance the CP's profit and avoid SLA violation. Numerical analysis stresses the ability of our approach to avoid SLA violation while maximizing the CP's profit under varying cloud environment conditions.

This paper presents a new technique for the minimization of I/O delay in the architectural synthesis of cyclic data flow graphs (DFG) representing DSP algorithms taking into consideration the inter-processor communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (throughput) with non-negligible inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshall's longest path algorithm so that the inter-processor communication overhead is taken into consideration to provide an optimized time and processor schedule. Moreover, the proposed scheme is applied to well- know DSP benchmarks and seen that it is efficient in minimizing the I/O delay without scarifying the iteration period.

A great deal of research has been conducted in the area of scheduling DSP data flow graphs (DFG) onto multiprocessor systems. This paper introduces a new scheduling and allocation algorithm for the synthesis of DSP applications. The proposed technique provides the designer with a greater flexibility to explore the design space using a hybrid arithmetic functional unit library composed of both fixed operation-specific units and reconfigurable functional units capable of executing multiple operations. A novel reconfigurable multiplier called morphable multiplier is incorporated in the proposed synthesis technique. We show that moving from a fully homogenous multiprocessor design using fixed multiple-operation units (i.e., ALUs) to a fully heterogeneous design using fixed operation-specific units (i.e., adders or multipliers) results in decreasing the area of the design, but increasing the inter-processor communication overhead. However, a hybrid multiprocessor architecture that uses a hybrid arithmetic functional unit library composed of both fixed operation-specific units and run-time reconfigurable multiple-operation units brings about a trade-off between the area and the inter-processor communication overhead