The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queuing and simulation methods. The model includes access conflicts at the bank level while assuming an ideal access network. A general scaling law is derived that indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is the average number of access requests arriving at a bank per bank reservation time. For light, uniform memory traffic. access delays are proportional to the square of the bank reservation time and to the ratio of the number of active memory access streams to the number of memory banks. With an assumption of random access patterns, an open and a closed queuing model are developed. To model pipelined access operations a new negative feedback model is introduced that includes the open and the closed models as special cases and is also well suited for modeling linked access streams. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads. The queuing models are validated by simulations.>

Delays caused by memory access conjiicts were measured for vector operations on the CRAY Y-MP and CRAY X-MP, and on two versions of the CRAY-2 with static and dynamic memory.The delays were measured as jimctions of vector length and the number of active processors.The observed delays were lowest for memory access operations with stride one.Considerably higher delays were observed for mixed strides or random access.For access operations with mixed strides, measurements indicate that memory access was slowed down by a factor of up to 1.7 for the 8-processor CRAY Y-MP.For the 4processor machines, the factors were 3.1 for the CRAY X-MP, 4.4 for the CRAY-2 with dynamic memory, and 2.5 for the CRAY-2 with static memory.The results are compared with a queueing model of memory bank conjiicts.A model of vector performance with vector loop unrolling is presented as a special case of a previously published model.

article A close look at vector performance of register-to-register vector computers and a new model Share on Authors: Ingrid Y. Bucher Los Alamos National Laboratory, Los Alamos, New Mexico Los Alamos National Laboratory, Los Alamos, New MexicoView Profile , Margaret L. Simmons Los Alamos National Laboratory, Los Alamos, New Mexico Los Alamos National Laboratory, Los Alamos, New MexicoView Profile Authors Info & Claims ACM SIGMETRICS Performance Evaluation ReviewVolume 15Issue 1May 1987 pp 39–45https://doi.org/10.1145/29904.29911Online:01 May 1987Publication History 11citation218DownloadsMetricsTotal Citations11Total Downloads218Last 12 Months5Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Problems related to the evaluation of computational speeds of supercomputers are discussed. Measurements of sequential speeds, vector speeds, and asynchronous parallel processing speeds are presented. A simple model is developed that allows us to evaluate the workload-dependent effective speed of current systems such as vector computers and asynchronous parallel processing systems. Results indicate that the effective speed of a supercomputer is severely limited by its slowest processing mode unless the fraction of the workload that has to be processed in this mode is negligibly small.