Microelectromechanical systems contain mechanical elements coupled with conditioning electronics that control and process the signal generated by the mechanical component. These systems are miniature and can be easily integrated on one chip, which explains the enormous popularity of MEMS. The applications of MEMS began with environmental sensors and have grown to encompass RF and optical applications along with energy harvesting. Because of their mixed-domain nature, the design of conditioning electronics relies on accurate models of the mechanical component. As an additional requirement, the model must be simple enough and be compatible with common circuit simulation tools. The latter requirement may be particularly difficult to achieve due to the fact that most of modern MEMS structures are quite complex and often nonlinear. In this conference contribution, we describe the methodology of building a model of a nonlinear MEMS resonator using the conventional modelling approach and then using an improved model together with an optimisation technique on the basis of the circuit simulator PAN.

The INSPEX H2020 project main objective is to integrate automotive-equivalent spatial exploration and obstacle detection functionalities into a portable/wearable multi-sensor, miniaturised, low power device. The INSPEX system will detect and localise in real-time static and mobile obstacles under various environmental conditions in 3D. Potential applications range from safer human navigation in reduced visibility, small robot/drone obstacle avoidance systems to navigation for the visually/mobility impaired, this latter being the primary use-case considered in the project.

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.

Compact MOSFET models for circuit simulation face several competing requirements, such as fast execution times, good accuracy and small memory requirements. This paper describes novel interpolation methods for accurate evaluation of MOSFET characteristics in weak, moderate, and strong inversion regions. These methods form the basis of a new table look-up model implemented in SPICE3F5. The table model provides great flexibility in adjustment of the simulation accuracy, speed, and memory consumption by providing a choice of interpolations and data tables. Application of the model to circuit simulation gives very accurate results in dc, transient, and ac analyses.

A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented.>