Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and key expansion. The estimated power results show that our implementation may achieve an energy per bit comparable with the lightweight standardized algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of 28 Mb/s in ST FDSOI 28-nm technology. In terms of security evaluation, our proposed datapath, 32-b key out of 128 b cannot be revealed by correlation power analysis attack using less than 20 000 traces.

Occupancy Grids (OGs) are a popular framework for robotic perception. They were recently adopted for performing multi-sensor fusion and environment mapping for autonomous vehicles. However, high computational requirements strongly hinder their integration into less powerful automotive ECUs. To overcome this problem, we propose an algorithmic improvement for mapping range measurements into OGs. Experiments were conducted on a vehicle equipped with 16 LIDAR scans. Results demonstrate that a single-core ARM cortex A9 can build now in real-time OGs that map urban traffic scenarios of 100m-by-100m.

For the last 25 years, occupancy grids have been intensively used as a well-understood framework for many robotic applications, such as path planning or obstacle avoidance. They offer a unifying framework for multiple heterogeneous sensor integration using a probabilistic representation of sensor data. This integration is computed through Bayesian techniques or evidence combination approaches, both requiring high computation workload using real number representation. In critical application domains, it is challenging to fuse data coming out of several sensors in real-time using constrained embedded platforms. In this paper, we propose a revised theoretical formulation of multi-sensor fusion using only integer arithmetic. We apply this novel framework to compute occupancy grid by only using integer numbers to represent probabilities. Compared to the state-of-the-art solutions, our fusion framework enables implementation on platforms with no floating-point support. Our experiments demonstrate that fusion of real automotive data from a 4-scans LIDAR can be integrated into a microcontroller without a floating-point unit. Our approach opens the perspective for microcontroller or even for hardware block based on ASIC or FPGA to support occupancy grid applications with real-time performance.

The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.

Technological advances have made wireless sensor nodes cheap and reliable enough to be brought into various application domains. These nodes are powered by battery, thus they have a limited lifespan which is a major drawback for their acceptance. This paper addresses a power consumption control problem of wireless nodes equipped with batteries. Dynamic power management is used to dynamically re-configure the set of sensor nodes in order to provide given services and performance levels with a minimum number of active nodes and/or a minimum load on such components. The power control formulation is based on model predictive control with constraints and binary optimization variables, leading to a mixed integer quadratic programming problem. Simulations are performed to demonstrate the efficiency of the proposed control method.

Power management is a hot-topic in complex System-on-Chip (SoC) designs. In the context of advanced technologies, Dynamic Voltage-Frequency Scaling (DVFS) techniques are widely proposed to improve efficiency. Nowadays, these mechanisms are composed of independent actuators controlling the applied voltage and clock frequency. A predefined sequence has to be used to switch from one state to another in order to avoid timing faults but increasing the energy cost. The timing of the sequence depends on the dynamic response of actuators. In this work, an external controller is designed in order to couple both actuators to manage the voltage and frequency transient periods, increasing power efficiency. The proposed controller has been implemented to couple a Vdd-hopping mechanism with a Frequency-Lock Loop circuit.

Compute-intensive applications can greatly benefit from the flexibility of NoC-based heterogeneous multi-core platforms. However, mapping applications on such MPSoC is becoming increasingly complex and requires integrated design flows. We conducted a case study to evaluate the benefits of an integrated design flow for the mapping space exploration of a real telecommunication application on a NoC-based heterogeneous platform. Thanks to the flow, we simulated several virtual platforms and several mappings of our application on each. This approach drastically lowers the required skills and the time needed for design space exploration. An improvement of several weeks have been observed.

While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This paper aims to present an overview of new, far-reaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.

In this paper we present an adaptive technique to locally adjust the frequency of processing elements on MP-SoC. The proposed method, based on game theory, optimizes the system while fulfilling dynamic constraints. A telecom test-case has been used to demonstrate the effectiveness of our technique. For the evaluated scenario, the proposed technique has obtained up to 20% of latency gain and 38% of energy gain.

We consider multiprocessor system-on-chip (MP-SoC) integrating several processing elements (PE). These architectures require distributed and scalable control techniques for run-time optimization of applicative parameters. Our approach is to use the game theory as an optimization model to solve the trade-off issues at run-time. We applied it to the distributed dynamic voltage frequency scaling (DVFS) management, adjusting at run-time the frequency set of each PE based on the synchronization between tasks of the application graph and the PE temperature profile. Results show that the analyzed algorithm converges to a solution in about 94% of the cases and in less than 40 calculation cycles for a 100-processor MP-SoC. It reaches an average optimization of 89% compared to an off-line centralized reference but about 140 times faster when simulating.