It is argued that introduction strategies for B-ISDN with a clear evolutionary path to the future must be worked out. Two strategies are described, along with their early application. The first is mainly intended for business customers and offers an initial-phase asynchronous transfer mode (ATM) cross-connect functionality. The second is for residential users and initially offers POTS (plain old telephone service) and narrowband ISDN and analog TV services. Both solutions can easily be upgraded step by step to a full ATM-based B-ISDN.>

The definition of a system requires the selection of a number of basic options. PTM (packet transfer mode) is a generic concept grouping a number of similar techniques which enable very flexible switching and transmission. The author describes the options and parameters which have been selected for a Belgian experiment planned in the early 1990s. Discussed are the following aspects: ATD (asynchronous time division) versus FPS (fast packet switching), including fixed or variable packet length, the optimal packet length, transmission and switching speed, and the number of lower-layer capabilities.>

This paper describes a switching network which is service independent and able to transport services of any bit rate, based on the fast packet switching concept. The control of the switching network is completely distributed; the path select is not centrally controlled, but gradually performed as the control packet is passing through the switching network. The switching network is a multistage network constructed with independent switching elements. The self-routing principle is applied. The load control of the different links between the switching elements in the network is provided by a static load control mechanism, applied to the logical connections granted on these links. Logical connections are accepted or rejected according to the already present load on each link. Possible overload caused by bursty traffic is solved by buffers within the switching elements. Simulation results are discussed, both for the static and dynamic behavior of the exchange. For both simulations, a large mix of different services is evaluated and conclusions are described.

The implementation of variable addressing and block structure has a substantial influence on the global system performance. One model dederibes this influence as a product of program statistical, architectural and technological parameters, but only for sequential processors. In this correspondence we adapt this model to processors with an instrution prefetch pipeline. An upper and lower bound for the performance measure is obtained, using a best/worst case analysis. The influence of the memory speed on the performance is also determined.

The knowledge of static and dynamic program statistics is indispensable for the efficient implementation of high level languages on a computer system. Several researchers have developed ad hoc measurement systems to collect various program statistics for one particular problem and one high level language.

Variable accesses and scope rule enforcements represent a major part of the execution time of block-structured high-level language programs. The performance of a computer system largely depends on the implementation of the variable addressing mechanism. Several lexical level addressing mechanisms exist to reduce this overhead, including the well-known display mechanism and a proposal by Tanenbaum. The choice among these mechanisms is not trivial, and requires a careful performance analysis.