In this paper, we present a new and effective approach to the extraction of on-chip inductance, in which we apply approximate formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs, in which most of the wires are not affected by the skin and proximity effects. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing runtime in the calculation of inductance while remaining accurate to within 3%. Within the geometrical constraints, the wires are of arbitrary specification.From a comprehensive evaluation on the ITRS-specified global wiring structure for 2003, the values for inductance extracted through the proposed approach are within 3% of the values obtained by commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

A MOSFET I-V model (MOSTSM) that is composed of simple analytical equations applicable down to a 0.5- mu m MOSFET operation is proposed. This model provides enhanced performance with respect to gate electric field effects on channel conductance and channel-length modulation in saturation operation. Subthreshold conduction is modeled, and simple and accurate geometrical effect (channel length; L) formulations for the model equations are developed. Features of the model are channel-length dependency of threshold voltage and effective channel conductance. A formulation of body factor on device threshold (K/sub b/) is proposed as a function of channel length. Experiments were conducted using various devices to demonstrate the model accuracy. The experimental results show that the MOSTSM model ensures curve-fitting accuracy within 1% for maximum average error over biases, even when the geometry effects are included. The devices used in the experiments were in the 0.5-2.0- mu m range of CMOS fabrication technology.>

Charge-conservative CV models for the MOSFET can be classified into two categories: a depletion charge model, which is accurate but complex, and a simplified charge model, which is less accurate but is very simple. The accuracy of the latter model is investigated. The model error of C/sub BD/ and C/sub BS/ is found to be between 10 and 26 percent even in a long-channel MOSFET. The model of the bulk charge Q/sub B/ causes this error. A simple but accurate model for C/sub BD/ and C/sub BS/ is found, and a model named MOSTSM is developed. The model accuracy for a 0.8- mu m nMOSFET is investigated. CV model error is found to be less than 10%. This model has been implemented in a circuit simulator.>

VLSI yield optimization and design centering are two key interests in the development of submicron VLSI's. Accordingly, we have developed a new design automation technique based on simulation CAD tools. The features of this methodology are great reduction of simulation time in device optimization, and accurate prediction of process sensitivity in device performance. The approach we used was basically a modification of the "design of experiment" method. This approach makes it possible to obtain an optimum design with a large number of design parameters. The methodology was successfully applied to the optimization of a 0.5-μm MOSFET structure based on only a one-day computation by a supercomputer (S-810) using a two-dimensional device simulator. In the design centering, we assumed five objective device performances, that is, threshold voltage V/sub TH/, output conductance G/sub D/, drain current I/sub D/, V/sub TH/ dependence on gate length ΔV/sub TH/ / ΔL/sub G/, and maximum substrate current I/ sub submax/. The use of the device design centering system predicted an optimized nMOSFET with 0.52-μm gate length, 9.4-nm gate oxide thickness, and 1.6 x 10/sup 16/cm/sup-3/ substrate concentration for a given set of objective performances. Statistical variations of device characteristics were also calculated.

A new two-dimensional integrated process simulation system named SPIRIT-I (Simulation Processor for Integrated Representation of Impurity-profile and Topography-I) has been developed. This system includes elementary process simulators of deposition, lithography, etching, ion implantation, diffusion, and oxidation. SPIRIT features a closely coupled simulation between a topography simulator and impurity-profile simulators at each processing step. As an example of simulation, an LDD (Lightly-Doped Drain) MOSFET with tilted source and drain implantation has been derived. In addition, this process simulation system is closely connected with a 3D device simulator. Using this coupled simulation system, the critical effect of processing conditions on device characteristics is analyzed.

A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can be obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFET's can be readily simulated with good convergence and good agreement with experimental results.