A multiple-output Boolean minimization procedure is presented that generates a minimum cover with computational efficiency by extending the directed search algorithm to the multiple-output case. This procedure is applicable to manual execution as well as to automated execution, and to both conventional two-level gating structures and programmable logic arrays (PLAs).>

The key to the effectiveness of any CAD system is the effectiveness of its human interface. Designers need an interface that is easily mastered, consistent across the variety of tools within the system, and adaptable. In an effort to provide this type of interface, the authors and others within the MCC CAD Program have built a software platform that isolates the input/output functions used by each CAD tool from the software of the tool itself. This platform includes a grammar-driven front end which supports 'modeless' input and standardized subsystems for graphical input and output. Use of this platform is supported by a suite of utilities that simplify the effort required of the CAD tool developer in specifying a user interface.

Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.

The fan-in and fan-out limitations imposed by specific gate circuits force corresponding limits-upon the sizes of carry lookahead circuits fabricated from those gates. The relationships between those limits are derived, providing simple formulae that can be used by designers seeking to fabricate fast combinational binary adders.

At the present time substantial software, memory, and CPU cycle penalties are incurred in bridging the semantic gap between high-level language formatted output statements and I/O device capabilities. Because of this gap and in response to the rapidly expanding capability of VLSI microelectronic circuits, a dedicated I/O processor is proposed to off-load the inherent conversion and formatting task from the host computer. The research reported here investigated the feasibility, the architectural requirements, and the implementational considerations of a regular design methodology for a VLSI-based I/O formatter.