Face Super-resolution is a challenging problem involving reconstructing High- Resolution (HR) images from Low-Resolution (LR) inputs with attention mechanisms being a widely used approach. This paper introduces counterfactual attention learning (CAL), a novel framework based on causal inference that enhances attention quality in super-resolution tasks. CAL provides a strong supervisory signal, enabling the refinement of attention mechanisms during training. Through counterfactual interventions, CAL optimizes learned attention to improve super-resolution outcomes. This method is evaluated using the Scale- Arbitrary Super-Resolution model (ArbSR), which accommodates non-integer scale factors. Experiments conducted on CelebA, FFHQ, and CMU Multi-PIE datasets across different scale factors show that CAL significantly enhances super-resolution performance. On the CMU Multi-PIE dataset, CAL improves Peak Signal-to-Noise Ratio (PSNR) by up to 13.6 % compared to baseline attention mechanisms, even under challenging variations in illumination, pose, and expression. PSNR improvement of 15.5 % was observed for CelebA dataset whereas for the FFHQ dataset, 14.5 % improvement was observed under occlusion conditions. These results highlight the robustness and effectiveness of CAL in advancing the state of super-resolution, offering substantial quantitative and qualitative improvements and showcasing its potential for face superresolution in real-world conditions.

This paper proposes design of a memristive crossbar array using the VTM-NAND logic gate. The novelty of this work is its diagonal computations using the proposed cellular arrangement to implement various logical functions. Some circuit examples are given and simulated using SPICE model of memristor with nonlinear dopant drift and 180 nm complementary metal oxide semiconductors (CMOS) technology.

We propose a novel Physical Unclonable Function (PUF) derived from the neuron used in the octopus retina. The signature obtained from a single neuron has been utilized to extract digital fingerprints uniquely for every single neuron. The proposed circuit topology has been investigated from a theoretical standpoint targeting new hardware-based security mechanisms obtained from intrinsic variations in the fabrication process of Spiking Neural Networks (SNNs). The uniformity, robustness and reliability of the proposed PUF have been verified by mean of the proposed analytical models aiming at developing new methodological approaches for the design of secure PUFs resilient to the adversarial Machine Learning attacks.

Spiking neurons, the models that mimic the biological cells in the brain, are described using ordinary differential equations. A common method to numerically solve these equations is Euler's method. An important factor that has a significant impact on the performance and cost of the hardware implementation or software simulation of spiking neural networks and yet its importance has been neglected in the published literature, is the time step in Euler's method. In this paper, first the Izhikevich neuron's accuracy as a function of the time step was measured. It was uncovered that the threshold time step that Izhikevich neuron becomes unstable is an exponential function of the input current. Software simulation performance, including total computational time and memory usage were compared for different time steps. Afterwards, the model was synthesized and implemented on the Filed Programmable Gate Array (FPGA). Hardware performance metrics such as speed, area and power consumption were measured for each time step. Results indicated that time step has a negative linear effect on the performance. It was concluded that by determining maximum input current to the neuron, larger time steps comparable to those used in the previous works could be employed.

Summary form only given. This paper proposes a neuromorphic platform for on-FPGA online Spike Timing Dependant Plasticity (STDP) learning, based on the COordinate Rotation DIgital Computer (CORDIC) algorithms. The implemented platform comprises two main components. First, the Izhikevich neuron model is modified for implementation using the CORDIC algorithm, simulated to ensure the model accuracy, described as hardware, and implemented on FPGA. Second, the STDP learning algorithm is adapted and optimized using the CORDIC method, synthesized for hardware, and implemented to perform on-FPGA online learning on a network of CORDIC Izhikevich neurons to demonstrate competitive Hebbian learning. The implementation results are compared with the original model and state-of-the-art to verify accuracy, effectiveness, and higher speed of the system. These comparisons confirm that the proposed neuromorphic system offers better performance and higher accuracy while being straightforward to implement and suitable to scale.

This paper addresses the problem of sensor selection in a sensor network for tracking a moving target. By considering network uncertainties and unpredictable movements of the target, reliable sensor selection approaches such as sigma points probability and target trajectory are proposed. An updated unscented Kalman filter is proposed to achieve effective tracking of the target through the sensor selection. A multialgorithm genetically adaptive multiobjective is utilized to have a selection strategy without knowing the number of sensors to be selected. Extensive experiments are conducted to evaluate the effectiveness of the proposed approach both in simulation and practical experimentation. The proposed algorithm is also tested in the industrial setting where providing safety is of great importance for a human worker who walks in a potentially dangerous workplace. The results confirm the effectiveness and utility of the proposed scheme.

This paper presents low cost, accurate and configurable digital circuits for pair-based and triplet-based STDP learning models, and the proposed architectures are compared with the state of the art approaches such as Lookup table (LUT), and Piecewise Linear approximation (PWL). Experimental results and error measurements indicate a maximum error of 0.0088 between the proposed digital circuits and the original learning models. The circuits have been synthesized and physically implemented on Altera FPGA board. Synthesis results verify that the proposed circuits take maximum 1% of the FPGA resources. The circuits can be employed in a large scale Spiking Neural Network (SNN) implementation due to their compactness and configurability.

Design for Testability (DfT) techniques allow devices to be tested at various levels of the manufacturing process. Scan architecture is a dominantly used DfT technique, which supports a high level of fault coverage, observability and controllability. However, scan architecture can be used by hardware attackers to gain critical information stored within the device. The security threats due to an unrestricted access provided by scan architecture has to be addressed to ensure hardware security. In this work, a solution based on the Clock and Data Recovery (CDR) method has been presented to authenticate users and limit the access to the scan architecture to authorized users. As compared to the available solution the proposed method presents a robust performance and reduces the area overhead by more than 10%.

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that utilize a gating structure by access devices to reduce sneak path effect. This paper has considerably lower wiring density and lower number of memristors per bit compared with its peers. Therefore, it can be a suitable structure for high-density memory and logic applications. In addition to its in-memory computing capabilities, 2M1M structure as a memory offers higher density and less energy consumption in comparison with conventional CMOS-based static random access memory. In comparison with previous works, simulation results show significant improvements in basic implementation costs of the memory cell in terms of write time (1.11 ns), read time (200 ps), density (80 Gb/cm2), energy consumption (23.2 × 10-3fJ/bit), and wiring complexity. Also, it has a sneak path current of 90-nA per memory cell operation which is considerably lower compared with its peers.

These days, there is an increasing interest in implementation of spiking neural systems that can be used to perform complex computations or solve pattern recognition tasks like mammalian neocortex. In this paper, Morris-Lecar neuron neuron is utilized to implement bio-inspired memristive spiking neural network for unsupervised learning applications. The spike timing dependent plasticity learning mechanism has been applied as the learning scheme in the system. The memristive implementation of the Morris-Lecar neuron has been analyzed. Also the memristors are utilized as the synapses for the proposed system to reproduce long term potentiation and long term depression. The proposed platform is tested for pattern classification applications and the results are successfully confirmed its functionality.

There is a tradeoff between the requirements for security and testability for a sensor node hardware. To test a sensor, it is desired to have access to the internal circuitry of the Device-Under-Test (DUT) to apply test stimuli and observe its responses. While such unrestricted access to the DUT is desired for testing, it can undermine the security. To secure a sensor node from attacks by malicious attackers, it is imperative to limit user access once the device has been adopted for in-field use. Efficient design-for-testability (DFT) techniques have been developed without taking into consideration the security threats posed by them. For instance, scan structure which is widely deployed in modern digital circuits, can be used as an effective tool to wage an attack and extract critical information from cryptographic cores. In this work, a new solution is presented to protect sensor nodes containing crypto-cores against scan-based attacks without compromising their testability at the manufacturing phase. In the proposed solution, a built-in self-test (BIST) technique is developed to carry out in-field tests for crypto-cores while a scan-based test method is utilized for manufacturing test. The proposed method prevents scan-based attacks without compromising testability during the manufacturing phase.

Two digit-level finite field multipliers in F2musing redundant representation are presented. Embedding F2min cyclotomic field F2(n)causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported.

In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for a digit-serial finite field multiplier in GF(2m). In the proposed design, a factoring technique is used to minimize switching power. To the best of our knowledge, factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. Logic gate substitution is also utilized to reduce internal power. Our proposed design along with several existing similar works have been realized for GF(2233) on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes at least 27.8% lower total power than any previous work in comparison.

This paper presents a Genetic Algorithm (GA) based evolution framework in which Spiking Neural Network (SNN) of single or a colony of artificial creatures are evolved for higher chance of survival in a virtual environment. The artificial creatures are composed of randomly connected Izhikevich spiking reservoir neural networks. Inspired by biological neurons, the neuronal connections are considered with different axonal conduction delays. Simulation results prove that the evolutionary algorithm has the capability to find or synthesis artificial creatures which can survive in the environment successfully and also simulations verify that colony approach has a better performance in comparison with a single complex creature.

Astrocyte as one of the brain cells controls synaptic activity between neurons by providing feedback to neurons. A novel digital hardware is proposed for neuron-synapse-astrocyte network based on the biological Adaptive Exponential (AdEx) neuron and Postnov astrocyte cell model. The network can be used for implementation of large scale spiking neural networks. Synthesis of the designed circuits shows that the designed astrocyte circuit is able to imitate its biological model and regulate the synapse transmission, successfully. In addition, synthesis results confirms that the proposed design uses less than 1% of available resources of a VIRTEX II FPGA which saves up to 4.4% of FPGA resources in comparison to other designs.

In this paper we propose a hardware implementation of a new deep brain stimulator that is able to desynchronize an abnormally synchronized neural population model. The proposed stimulator is based on a delay feedback technique and is applied on a population of neurons described with Izhikevich model. The whole structure of the stimulator and the neural population model are first simulated in software and then implemented on hardware FPGA platform. The results of software/hardware simulation/implementation show that the proposed stimulator has a good performance and is able to desynchronize a hyper-synchronized neuronal population model.

Memristor-based arithmetic circuits promise new alternatives for their conventional CMOS-based peers due to memristor' s scalability and non-volatility features. In-memory memristor-based calculations become extensively attractive as it can be a solution to tackle memory bottleneck problems and also an ingredient for future beyond Von-Neumann computer architectures. In this paper material implication-based designs for 4:2 compressor cells using memristor devices are presented. A physical model is applied to determine real switching speed of memristive device. The proposed parallel design promises good speed performance with considerably less area than conventional CMOS designs. Finally a comparison has been made between the proposed memristor-based and CMOS-based designs in terms of number of applied devices per cell and delay.

Many high dimensional data mining applications involve the nearest neighbor search (NNS) on a KD-tree. Randomized KD-tree forest enables fast medium and large scale NNS among high dimensional data points. In this paper, we present massively parallel algorithms for the construction of KD-tree forest, and NNS on a cluster equipped with massively parallel architecture (MPA) devices of graphical processing unit (GPU). This design can accelerate the KD-tree forest construction and NNS significantly for the signature of histograms of orientations (SHOT) 3D local descriptors by factors of up to 5.27 and 20.44, respectively. Our implementations will potentially benefit realtime high dimensional descriptors matching.

In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication and secret key generation. The proposed circuit is designed and simulated in 45-nm bulk CMOS technology. Monte Carlo simulation for this circuit, results in unpolarized Gaussian-shaped distribution for Hamming Distance between 4005 100-bit PUF instances.

In this paper design and implementation of a modular mixed-signal feed-forward neural network is presented. The network is implemented based on the Continuous Valued Number System (CVNS) arithmetic with neurons distributed in the network. Synapse weights are implemented on the chip using capacitive analog memories. Weight values are stored as the CVNS values and are refreshed and updated using the overlap between the CVNS digits. Current-mode logic is used for implementation in order to simplify the circuit design, and especially addition, which resulted in reduced power and area consumption. The distributed nature of the neurons allows for expansion of the network into larger networks. Individual modular layers are fabricated in TSMC CMOS 180nm, and are used to form different network sizes. The module is used to configure two proof of concept examples, a 2 - 2 - 1 and a 3 - 2 - 1 network to solve the XOR problem. Results of test and verification presented in this paper show the network flexibility of the proposed design to form various network configurations.

This paper presents parallel algorithms for the construction of k dimensional tree (KD-tree) and nearest neighbor search (NNS) on massively parallel architecture (MPA) of graphics processing unit (GPU). Unlike previous parallel algorithms for KD-tree, for the first time, our parallel algorithms integrate high dimensional KD-tree construction and NNS on an MPA platform. The proposed massively parallel algorithms are of comparable quality as traditional sequential counterparts on CPU, while achieve high speedup performance on both low and high dimensional KD-tree. Low dimensional KD-tree construction and NNS algorithms, presented in this paper, outperform their serial CPU counterparts by a factor of up to 24 and 218, respectively. For high dimensional KD-tree, the speedup factors are even higher, raising to 30 and 242, respectively. Our implementations will potentially benefit real time three-dimensional (3D) image registration and high dimensional descriptor matching.

In this paper, design of a passive resistive-type neuron is proposed to generate the hyperbolic tangent function as the activation function. The proposed resistive-type neuron has the advantage of not needing any biasing voltage and therefore its power consumption is low. The neuron circuit is designed and simulated in 180 nm CMOS technology. The proposed neuron shows a good approximation with maximum error and average error from the ideal hyperbolic tangent function by 19.7% and 6.88% respectively. The power consumption of the proposed neuron is 62.5 μW while the standby power is zero. Also the proposed neuron is applied in a large neural network and the results shows good functionality. The pattern recognition neural network implemented using the proposed neuron is consumed 295 μW power that is approximately 59.86% less than the same network proposed with the previous analog hyperbolic tangent designed neuron.

A local‐based illumination insensitive face recognition algorithm is proposed which is the combination of image normalisation and illumination invariant descriptors. Illumination insensitive representation of image is obtained based on the ratio of gradient amplitude to the original image intensity and partitioned into smaller sub‐blocks. Local phase quantisation and multi‐scale local binary pattern, extract the sub‐regions characteristics. Distance measurements of local nearest neighbour classifiers are fused at the score level to find the best match and decision‐level fusion combines the results of two matching techniques. Entropy, class posterior probability and mutual information are utilised as the weights of fusion components. Simulation results on the YaleB, Extended YaleB, AR, Multi‐PIE and FRGC databases show the improved performance of the proposed algorithm under severe illumination with low computational complexity and no reconstruction or training requirement.

This work presents a GPU implementation of the Montgomery multiplication algorithm that is heavily optimized for the GPU's SEVID architecture, as well as the field sizes and constraints required for elliptic curve cryptography. We present and compare the throughput results of our proposed algorithm for 10 commonly used field sizes from 112 to 521 bits. When executed by our NVIDIA GTX-480 GPU device, the proposed algorithm's measured throughput in multiplication operations per second is 1.24 to 1.72 times greater than the next fastest GPU-based algorithm running on the same device, and is significantly greater than all other published CPU and GPU-based implementations. The proposed work could be used as a component of an elliptic curve cryptography acceleration appliance, or for cryptanalysis.

Neural Networks have been widely used in face recognition as a reliable classifier. In the proposed method, neural network classifier with CSD coefficients is used to speed up the recognition system. The FPGA implementation of the proposed method indicates that the high speed recognition can be achieved by using neural network classifier with CSD coefficients while maintaining good recognition rate.

In this paper, we present a new readout circuit with an integrated built-in self-test (BIST) structure for capacitive microelectromechanical system (MEMS). In the proposed solution, instead of commonly used voltage control signals to test the device, charge-controlled stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of structural collapse in the test phase for gap-varying parallel-plate MEMS devices. Measurement results using a prototype fabricated in TSMC 65-nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance.

Testing the integrity of interconnects realized by through silicon vias (TSVs) in 3-D integrated circuits (3-D IC) is considered a challenging task. TSVs are excessively small and fragile for current probe technology. In this paper, a new spring-type probe using microelectromechanical systems (MEMS) technology is presented. The implemented MEMS probe supports the required pitch for TSV direct probing and minimizes the undesired scrub marks on TSV surface. Simulation results indicate that the implemented MEMS probe can operate at the gigahertz frequency range without significant test signal degradation.

This paper presents a high performance algorithm for modular multiplication on a graphics processing unit (GPU) implemented in assembler. The proposed algorithm carries out finite field multiplication over the NIST prime fields of size 192, 224, 256 and 384 bits. Included is a detailed explanation of our algorithm, an instruction count analysis, and a comparison to recently published work; compared to the next fastest design, the proposed algorithm's execution time is 27 to 71 times faster.

Normal basis has been widely used for the representation of binary field elements mainly due to its low-cost squaring operation. Optimal normal basis type II is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications. In this paper, high-speed architectures for binary field multiplication using reordered normal basis are proposed, where reordered normal basis is referred to as a certain permutation of optimal normal basis type II. Complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type II or a reordered normal basis. One advantage of the new word-level architectures is that the critical path delay is a constant (not a function of word size). This enables the multipliers to operate at very high clock rates regardless of the field size or the number of words. Hardware implementation of some practical size multipliers for elliptic curve cryptography is also included.

An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC’s .18 um CMOS technology for the binary field size of 163 is also presented.

Radiometric degradation is a common problem in the image acquisition part of many applications. There is much research carried out in an effort to deblur such images. However, it has been proven that it is not always necessary to go through a burdensome process of deblurring. To tackle this problem, different blur-invariant descriptors have been proposed so far, which are either in the spatial domain or based on the properties available in the Fourier domain. In this paper, wavelet-domain blur invariants are proposed for the first time for discrete 2-D signals. These descriptors, which are invariant to centrally symmetric blurs, inherit the advantages that this domain provides. It is also proven that the spatial-domain blur invariants are a special version of the proposed invariants. The performance of these invariants will be demonstrated through experiments.

An important part of any hardware implementation of artificial neural networks (ANNs) is realization of the activation function which serves as the output stage of each layer. In this work, a new NMOS/PMOS design is proposed for realizing the sigmoid function as the activation function. Transistors in the proposed neuron are biased using only one biasing voltage. By operating in both triode and saturation regions, the proposed neuron can provide an accurate approximation of the sigmoid function. The neuron circuit is designed and laid out in 90-nm CMOS technology. The proposed neuron can be potentially used in implementation of both analog and hybrid ANNs.

Distributed Neural Networks (DNNs) are generally providing self-scaling property together with higher noise immunity for resistive-type neural networks. Continuous Valued Number System (CVNS) is a potential candidate to build the DNNs; however, implementation of a CVNS digit in its complete form needs a high resolution environment which is not practical. Truncation methods are applied to CVNS digits to make them adaptable to the low resolution environments. However, truncated CVNS operations may decrease the accuracy and immunity to noise compared to the complete CVNS operations. In this work, a truncated CVNS DNN is proposed, and studies over Noise to Signal Ratio (NSR) and accuracy are provided. Studies show that the accuracy is acceptable, and the NSR is still less than the NSR of conventional DNNs.

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-level finite field multiplier using normal basis is proposed. The proposed architecture takes d clock cycles to compute the product bits, where the value for d, 1\leq d \leq m, can be arbitrarily selected by the designer to set the tradeoff between area and speed. When there exists an optimal normal basis, it is shown that the proposed design has a smaller critical path delay than other word-level normal basis multipliers found in the literature, while its circuit complexities are moderate and comparable to the others. Different word size multipliers were implemented in hardware, and implementation results are also presented.

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

A new method for face recognition based on weighted votes on different sub-images of a picture is proposed. The proposed method is robust under illumination variations and achieves the illumination invariants based on the reflectance-illumination model. The proposed method does not require any prior information about the face shape or illumination and can be applied on each image separately. It does not need multiple images in training stage to get the illumination invariants and is computationally efficient. Support vector machines are used as classifier. Several experiments are performed on Yale B and CMU-PIE databases. The system achieved 99.82% recognition rate in the Yale B and 99.74% for the CMU-PIE database.

In the area of signal processing, digital circuits are advantageous in terms of lower sensitivity to noise and process variations, simplicity of design, programmability and test, while they attain higher speed, more functionality per chip, lower power dissipation or lower cost. Since some of DSP algorithms heavily rely on multiplication, there are constant demands for more efficient multiplication structures. In this paper, 2DLNS-based multiplication architectures with two different levels of recursion are presented. Our architectures combine some of the flexibility of software with the high performance of hardware through implementing the recursive multiplication schemes on a 2DLNS processing structure. The implementations demonstrate the efficiency of 2DLNS in DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.

The trade-off between pedestal error and acquisition time limits the level of speed-accuracy that can be achieved by CMOS track-and-hold circuits. This paper presents a circuit technique to design a high-resolution, high-speed T/H circuit. The sampling error produced by clock feedthrough and the charge injection of CMOS switches are eliminated through a cancellation technique using a replica circuit. Simulation results using CMOS 90 nm process confirm that the proposed method lowers the pedestal error considerably and supports linearity over 9.8 effective bits at 500 MHz sampling rate for input signals up to 10 MHz.

In this paper, a multiple-valued DRAM is proposed. Error correction has been used to increase the noise margin of the system. The refresh system is based on series configuration of A/D and D/A converters for each data line. The A/D converters are based on a modular reduction operation, which provides an area efficient design. This memory cell can be used in hardware implementation of multiple valued neural networks.

Efficient implementation of the activation function is important in the hardware design of artificial neural networks. Sigmoid, and hyperbolic tangent sigmoid functions are the most widely used activation functions for this purpose. In this paper, we present a simple and efficient architecture for digital hardware implementation of the hyperbolic tangent sigmoid function. The proposed method employs a piecewise linear approximation as a foundation, and further improves the results using a lookup table. Our design proves to be more efficient considering area times delay as a performance metric when compared to similar proposals. VLSI implementation of the proposed design using a 0.18 mum CMOS process is also presented, which shows a 35% improvement over similar recently published architectures.

Data clustering plays an important role in many disciplines, including data mining, machine learning, bioinformatics, pattern recognition, and other fields. When there is a need to learn the inherent grouping structure of data in an unsupervised manner, ant-based clustering stand out as the most widely used group of swarm-based clustering algorithms. Under this perspective, this paper presents a new Adaptive Ant-based Clustering Algorithm (AACA) for clustering data sets. The algorithm takes into account the properties of aggregation pheromone and perception of the environment together with other modifications to the standard parameters that improves its convergence. The performance of AACA is studied and compared to other methods using various patterns and data sets. It is also compared to standard clustering using a set of analytical evaluation functions and a range of synthetic and real data collection. Experimental results have shown that the proposed modifications improve the performance of ant-colony clustering algorithm in term of quality and run time.

In this paper, we propose a wavelet based feature extraction method with a high tolerance to white Gaussian noise. This method is also computationally efficient. Along with an HMM classifier, this method is used for face recognition. High recognition rates in the presence of white Gaussian noises with different variances show this technique as a promising feature extraction method.

In this paper, a high-speed word level finite field multiplier in F2musing redundant representation is proposed. For the class of fields that there exists a type I optimal normal basis, the new architecture has significantly higher speed compared to previously proposed architectures using either normal basis or redundant representation at the expense of moderately higher area complexity. One of the unique features of the proposed multiplier is that the critical path delay is not a function of the field size nor the word size. It is shown that the new multiplier outperforms all the other multipliers in comparison when considering the product of area and delay as a measure of performance. VLSI implementation of the proposed multiplier in a 0.18- mum complimentary metal-oxide-semiconductor (CMOS) process is also presented.

Machine vision systems provide quality control and real-time feedback for industrial processes, overcoming physical limitations and subjective judgment of humans. In this paper, the image processing techniques for developing low-cost machine vision system for pharmaceutical capsule inspection is explored. By developing image processing techniques, and using PCs, custom USB 2.0 cameras with minimal hardware, a low-cost flexible system is developed. This paper discusses the two-part gelatin capsule inspection system that belongs to USB camera 2.0 and associated hardware, the PCs to acquire the image data of the capsule, image processing techniques using border tracing and approximating the capsule to a circle to perform inspection and a custom system controller to pass the accepted and rejected capsules to the appropriate bin.

This paper presents a motion adaptive deinterlacing method for high quality conversion of interlace video format to progressive video format. A high performance and low complexity algorithm for motion detection is proposed. This algorithm uses five consecutive interlace video fields for motion detection, so it is able to capture a wide range of motions from slow moving objects to fast motions. The proposed motion detection algorithm benefits from a hierarchal structure where the algorithm starts with detecting motion in large partitions of a given field. Depending on the detected motion activity level, the motion detection algorithm might be recursively applied to sub-blocks of the original partition. Two low pass filters are used during the motion detection to increase the algorithm accuracy. The result of motion detection is then used in a motion adaptive interpolator for high quality deinterlacing. Excellent experimental results are obtained for motion detection and deinterlacing performance.

This paper presents a novel high-throughput algorithm for the H.264/AVC transforms. The symmetry property of transforms in H.264/AVC has been utilized. The straight forward method merges the conventional two-stage row-column algorithm into one-stage operation. By analysis and comparison, the proposed algorithm consumes less arithmetic operations (additions and shifts) and has less latency delay. It can complete any type of transforms of H.264/AVC in only one clock cycle. Besides, its regular processing element is reconfigurable. This method is suitable for reconfigurable hardware implementation.

This paper explores properties of an analog artificial neural network architecture based on Continuous Valued Number System (CVNS) with distributed neurons. In conventional lumped neural networks, the effect of weight quantization errors effects the performance of the network as the network size increases. However, based on a stochastic model it is shown here that the CVNS capability in detecting and correcting errors along with the inherent self-scaling property of distributed neurons, can control the output quantization noise to signal ratio. This property contributes to a robust analog VLSI architecture based on analog distributed CVNS-Adaline neurons.

Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered normal basis is presented. Proposed architecture has a very regular structure which makes it suitable for VLSI implementation. Architectural complexity comparison shows that the new architecture has smaller critical path delay compared to other word level multipliers available in open literature at the cost of having moderately higher area complexity. The new architecture out performs all other similar proposals considering the product of area and delay as a measure of performance.

A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower complexity and comparable critical path delay or a significantly smaller critical path delay and comparable complexity in comparison to the previously proposed architectures using the same representation. For the class of fields where there exists a type I optimal normal basis, the proposed multiplier compares favorably to the normal basis multipliers. A digit-level version for the new multiplier is also presented in this paper.

In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mum technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250mum2.

Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The Continuous Valued Number System (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An8×8digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS0.18μmtechnology, with a maximum delay of900ps, static power consumption of19mWand a core area of11200μm2. The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.

Content-Based Image Retrieval (CBIR) Systems are becoming increasingly important and finding application in diverse areas of discipline. Due to disturbing factors present in images, e.g. non-uniform illumination and lightening intensities, the retrieval results are not always satisfactory. In this paper, we discuss how fuzzy set theory can be used to formulate an efficient image signature. This signature is 1-D Fuzzy Color Histogram (FCH) consisting of a small number of bins. The signature is obtained from image contents by considering the contribution of each pixels color to all the histogram bins through the use of fuzzy-sets membership functions. Experimental results on a database of over 10,000 images demonstrate that the proposed system is less sensitive light intensity changes and more robust than the Conventional Color Histogram (CCH) in retrieval precision.

Two high-speed bit-serial word-parallel or comb-style finite field multipliers are proposed in this paper. The first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type-II optimal normal basis exists. The proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same. The proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis. Field-programmable gate array (FPGA) implementation results of the proposed multipliers are compared to those of the previous methods using the same basis, which confirms that the proposed multipliers allow a much higher clock rate.

This paper describes the test and measurement of high-frequency analog/RF cores in a mixed-signal system-on-chip (SoC) environment using an embedded tester core. A new test methodology has been developed in which high-frequency tests are performed on-chip, but the control and test results are transmitted over the lower bandwidth connectivity associated with the SoC I/O terminals. A low-frequency analog signal is used to modulate a high-frequency squarewave and the resulting waveform is applied to a high-frequency circuit-under-test (CUT) as a test stimulus. The CUT's response is sampled using a coherent subsampling technique and the captured samples are transmitted at low-speeds off-chip from the SoC. A coupled phase-locked-loop and delay- locked-loop structure is employed to generate test waveforms in the 2.7-GHz range and to support high-resolution sampling with a sampling resolution of less than 10 ps. Simulation results using a reference low noise amplifier as a CUT shows the effectiveness of the proposed test method. The tester core has been sent for fabrication in CMOS 0.18-mum technology with a target area of 1 mm2.

The binarization stage is a very critical in document analysis since the quality of a binarized image determines the performance of the entire process. However due to many uncertain factors such as complex signal-dependent noise and variable background intensity, which is caused by non-uniform illumination, shadow, smear, smudge or low contrast, an effective binarization algorithm that will work on a broad set of composite documents has yet to be developed. Here we propose a new algorithm which implements hidden Markov model in the binarization stage. The simulation results prove that this method is efficient in extracting information from various noisy backgrounds.

This paper presents a new algorithm for finding the point of correspondence in stereo images using a Hopfield neural network (HNN). A 2D HNN is used to match primitives extracted form one image to the other. The features used for this operation are edge points extracted using the Sobel operator. A formulation of the stereo correspondence as an optimization problem has been presented where various geometrical properties of multiple view geometry including disparity gradient (DG) have been used as constraints on the objective function. The 2D HNN is then used to minimize this function, thus achieving an optimum correspondence from one to the other image. The results show higher accuracy than template matching and local search methods

Histogram based thresholding methods are mainstream methods in the binarization of document images. However many uncertain factors such as complex signal-dependent noise and variable background intensity, which are caused by non-uniform illumination, shadow, smear, smudge or low contrast make it very difficult to obtain proper threshold through the histograms of images. This is caused by the shapes of the histograms which are arbitrary instead of being bimodal. In this paper we will propose a new edge based thresholding algorithm which converts the histograms of noisy images into bimodal, then it is possible to efficiently extract objects especially texture information from noisy background.

This paper aims to provide a restoration algorithm for the Pahlavi or middle-age Persian manuscript. This is the preliminary document processing view to this area. The central idea is based on the morphological analysis and connected component concept. The proposed algorithm uses the mathematical morphology and connected component concept to segment the line, word, and character overlapped Pahlavi documents and prepares those texts for OCR application. To evaluate the performance of the algorithm, it has been tested on 200 pages of the Pahlavi documents. The algorithm has a good success on document restoration and segmentation. Numerical results indicate that the proposed algorithm can remove the noise and destructive effects. The results also show 99.14% accuracy on the baseline detection, 97.35% accuracy on the text line extraction and removing other lines overlaps, and 99.5% accuracy for segmenting the extracted text lines to their components.

Pseudo-Zernike polynomials are well known and widely used in the analysis of optical systems. In this paper, a weighted Pseudo-Zernike feature is introduced for face recognition. We define a weight function based on the face local entropy. By this weight function, the role of high information region, i.e. eyes, noses and lips, will be intensified on the extracted features. For classification, a single hidden layer feedforward neural network has been trained. To evaluate the performance of the proposed technique, experimental studies are carried out on the ORL database images of Cambridge University. The numerical results show 98.5% recognition rate on the ORL database with the order 8 of weighted Pseudo-Zernike feature and 44, 98, 40 neurons for the input, hidden, and output layers while this amount is 96% for the original Pseudo-Zernike.

A simplification of the log-MAP algorithm for use in turbo decoders and turbo equalizers is presented. The simplified algorithm is based on the MacLaurin series expansion of the logarithmic term in the Jacobian logarithmic function used in the log-MAP algorithm. In terms of complexity the proposed algorithm can easily be implemented using adders and comparators as this is the case for the max-log-MAP algorithm. Also, simulation results show that the proposed algorithm has performance very close to the log-MAP algorithm for both turbo decoding and turbo equalization, even in a high loss intersymbol interference (ISI) channel where there is a wide gap between the performance of the log-MAP and max log-MAP turbo equalizers.

Contrast enhancement of the lateral skull X-ray images is very important in orthodontic practice, cephalometric evaluation and craniofacial landmarking. In this paper we present computational techniques involving contrast enhancement of two-dimensional digitized X-ray images. The algorithm is developed based on the use of local heterogeneity measures of pixel distribution. Image enhancement is accomplished by an adaptive gray scale pixels transformation depending on results of local heterogeneity contribution measures. The proposed approach was tested on different images and the results prove that the proposed method has better performance the existing conventional methods.

A new mixed-signal feed-forward neural network for pattern/shape recognition problems is proposed. The network has a mixed-signal structure, operations are performed in analog and weights are stored in digital. To increase the network robustness, on-chip training with Madaline Rule III is used. The proposed architecture uses time-multiplexing to increase the network density and resistive-type neurons for their self-scaling property. The results of an XOR network are presented to test the network.

This paper introduces an efficient method for the recognition of human faces in 2-dimensional digital images using a new feature extraction method. The proposed feature extraction method includes human face localization derived from the shape information using a new distance measure as facial candidate threshold (FCT) as well as Pseudo Zernike moment invariant (PZMI). Also we introduce a new parameter to define axis correction ratio (ACR) of images for disregarding irrelevant information of face images. In this paper the effect of the new parameters in disregarding irrelevant information in recognition rate is studied. Also we evaluate the effect of orders of PZMI in the proposed technique. Simulation results on the face database of Olivetti research laboratory (ORL) indicate that high order PZMI together with derived face localization and proposed technique for feature extraction contain very useful information about face recognition process. Recognition rate of 99.3% is obtained using this proposed technique.

This paper introduces a novel method for the recognition of human faces in two-dimensional digital images using a new feature extraction method and Radial Basis Function (RBF) neural network with a Hybrid Learning Algorithm (HLA) as classifier. The proposed feature extraction method includes human face localization derived from the shape information using a proposed distance measure as Facial Candidate Threshold (FCT) as well as Pseudo Zernike Moment Invariant (PZMI) with a newly defined parameter named Correct Information Ratio (CIR) of images for disregarding irrelevant information of face images. In this paper, the effect of these parameters in disregarding irrelevant information in recognition rate improvement is studied. Also we evaluate the effect of orders of PZMI in recognition rate of the proposed technique as well as learning speed. Simulation results on the face database of Olivetti Research Laboratory (ORL) indicate that high order PZMI together with the derived face localization technique for extraction of feature data yielded a recognition rate of 99.3%.

This paper presents a novel number system based on signed continuous valued digits. Arithmetic operations in this number system are performed using simple analog circuitry, in contrast to the conventional implementation of arithmetic units by Boolean or multiple-valued logic circuits. Unlike the limited precision offered by classical analog arithmetic circuits, the ensemble of continuous valued digits that comprises a number in this system provides arbitrary implementation precision with standard analog circuitry. The number system also provides almost-carry-free arithmetic structures with digit level redundancy. In this paper, we introduce the mathematical foundations for positive and negative numbers, addition, multiplication, redundancy, radix conversions, and also the digit value integrity for circuit implementations. Potential applications are in the area of low noise and low cross-talk circuitry for arithmetic circuits used in mixed-signal systems.

The rectilinear Steiner tree (RST) problem is of essential importance to the automatic interconnect optimization for VLSI design. In this paper, we present a class of probability-based approaches toward the best solutions under statistical sense and show their performance in comparison with the state-of-the-art algorithm. Experiments conducted on both small- and large-size problems indicate that the proposed approaches lead to promising results in terms of wire length and/or CPU time. The potential advantages with our technique are also discussed for further applications.

This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause $I_{DDQ}$ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.

A new algorithm based on Genetic Programming (GP) for the problem of optimization of Multiple Constant Multiplication (MCM) by Common Subexpression Elimination (CSE) is developed. This method is used for hardware optimization of DSP systems. A solution based on GP is shown in this paper. The performance of the technique is demonstrated in one- and multi-dimensional digital filters with constant coefficients.

This paper presents application of fusion techniques in a handwritten numeral recognition. The authors present two methods of fusing classifiers based on the fuzzy integral for handwritten numeral recognition. We also demonstrate that modification of fuzzy density calculation will result in better recognition rate. Test conducted on a large set of handwritten numeral data yielded high recognition rate with the proposed technique.

An unconstrained Farsi handwritten word recognition system based on fuzzy vector quantization (FVQ) and a hidden Markov model (HMM) for reading city names in postal addresses is presented. Preprocessing techniques including binarization, noise removal, slope correction and baseline estimation are described. Each word image is represented by its contour information. The histogram of chain code slopes of the image strips (frames), scanned from right to left by a sliding window, is used as feature vectors. Fuzzy c-means (FCM) clustering is used for generating a fuzzy code book. A separate HMM is trained by a modified Baum-Welch algorithm for each city name. A test image is recognized by finding the best match (likelihood) between the image and all of the HMM work models using a forward algorithm. Experimental results show the advantages of using an FVQ/HMM recognizer engine instead of conventional discrete HMMs.

A hybrid system for the recognition of handwritten Farsi words using self-organizing feature map, right-left discrete hidden Markov models, and evolutionary programming is presented. The histogram of chain-code directions of the image strips, scanned from right to left by a sliding window, is used as feature vectors. The self-organizing feature map is used for constructing the codebook and also smoothing the observation probability distributions. A population based approach using evolutionary programming with a self-adaptive Cauchy mutation operator is used to find an appropriate initial model as starting point for the classical Baum-Welch algorithm. Experimental results were found to be promising.

The design of a microelectromechanical (MEMS) device that forms part of a micro acousto-magnetic transducer for use with a hearing instrument is described in this paper. A MEMS realization of a microelectromagnetic actuator is used to generate a magnetic field that exerts a force on a permanent micromagnet that has been implanted on the round window of the cochlea. The motion of the implanted magnet will develop traveling waves on the basilar membrane inside the cochlea to give a hearing capability. A modular realization of the micro electromagnet has been proposed that offers the advantage that the magnet's magnetomotive force performance characteristics can be easily changed by depositing additional layers of the modular realization for the magnet core segments and their associated section of excitation winding. The MEMS structures have been designed and simulated using the IntelliSuite MEMS software package from the IntelliSense Corporation.

The synthesis of M-D filtering by using causal real coefficient MD all-pass blocks is formulated. The new architecture features excellent fixed-point behavior. A novel word parallel architecture for the design of 2-D digital filters is presented. The presented architecture is used for the design of 2-D digital all-pass filters for the purpose of general filtering. This architecture may easily be expanded for the realization of M-D filters.

A holistic system for the recognition of handwritten Farsi/Arabic words using right-left discrete hidden Markov models (HMM) and Kohonen self-organizing vector quantization is presented. The histogram of chain-code directions of the image strips, scanned from right to left by a sliding window, is used as feature vectors. The neighborhood information preserved in the self-organizing feature map (SOFM), was used for smoothing the observation probability distributions of trained HMMs. Experiments carried out on test samples show promising performance results.

This paper presents mathematical foundations of the Overlap Resolution Number System (ORNS) which is based on signed continuous valued digits (CVDs). ORNS is a redundant number system employing residue arithmetic. In contrast to the implementation of arithmetic by binary or multiple-valued logic circuits, arithmetic operations in this novel number system are performed by analog digit manipulation circuitry. The redundancy in an ensemble of continuous valued digits that comprises a number provides tolerance to implementation imprecisions. Processing with these analog digits is performed by carry-free arithmetic structures with systematic circuit level redundancy.

This paper provides a simulation-based study of the delay fault testing in logic circuits. It is shown that delay testing is necessary in order to achieve a high defect coverage. By detecting delayed time response in a transistor circuit, three types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects, (2) faults which cause an intermediate voltage level at the output node, and (3) most stuck-at faults which halt the circuit at '1' or '0'. An on-line checker is presented which enables the concurrent detection of delay faults. Since one checker is used for each output signal, the area overhead is minimal. This technique does not degrade the speed of the circuit under test (CUT). We show that the test circuit is independent of the size of the CUT. Simulation results show that this technique can be adjusted to fit to any design style.

In this paper, a technique for extracting the distortion parameters in filled-in forms is presented. The technique determines the transformations that is required to convert a filled-in form to match a known master and then extracts filled-in information. The method involves determining corresponding lines and keypoints between the master and the filled-in form and using the correspondence to determine the appropriate transformation. The correspondence problem is solved using results from geometric hashing voting scheme.

In this paper, a technique for extracting the distortion parameters in filled-in forms is presented. The technique determines the transformations that are required to convert a filled-in form to match a known master and then extracts filled-in information. The method involves determining corresponding lines and key points between the master and the filled-in form and using the correspondence to determine the appropriate transformation. The correspondence problem is solved using results from affine geometry.

A new algorithm for the extraction of words from printed documents that have interference marks and other strokes, cutting across text, is presented. Morphological operations based on multiple direction projection planes and skeleton images are adopted here to prevent the "flooding water" effect of conventional morphological operations. Test results indicate the feasibility of the proposed approach.

A technique for extracting filled-in information in form documents is presented. The transformation that is required to convert a filled-in form to match the master (blank form) is derived using results from projective geometry. Experimental studies with several forms indicate the proposed technique to be accurate and robust.

We describe the design and VLSI implementation of a unified synapse-neuron architecture for multi-layer neural networks. A new hybrid building block proposed for this purpose is formed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC synapse. MDAC synapse contains modifications to simplify sign-bit circuit. Small analog circuits generate a distributed S-shape neural function by combining quadratic characteristics of four MOS transistors. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problem, improved robustness and digital programmability. Based on the proposed scheme, we have considerably increased the synaptic density in the improved version of a programmable optically-coupled neural network.

A structure consisting of only all-pass subsystems for the design of n-dimensional IIR digital filters with arbitrary cutoff boundaries is presented. It is shown that an all-pass filter is a universal building block for multidimensional digital filter structures. Utilization of the proposed structure for n=2, and 3 is given in more detail.

In this paper, an evidence fusion technique, based on the notion of fuzzy integral is utilized to combine (fuse) the results of multiple character classifiers and realize a robust algorithm for high accuracy handwritten character recognition. Both source (classifier) relevance as well as source evidence are utilized to achieve significant enhancements. An algorithm for dynamically assigning source relevance, using the performance matrices of individual classifiers has also been developed. Experiments on a large data set show that a very low error rate and a low rejection rate can be achieved by fusing several simple classifiers.

This paper deals with the extraction of words from printed documents that have interference and other strokes (enclosing curves, underlines etc.). A new algorithm which combines the two processes of thinning and detection of directional strokes to effectively segment not only straight lines but also smooth arbitrarily oriented curves. The algorithms preserve both connectivity and directional characteristics. The morphological operations based on multiple direction projection planes and skeleton images are adopted here to successfully prevent the "flooding water" effect of conventional morphological operations. The effectiveness of the proposed algorithms is demonstrated on several experimental images.

In this paper a method for the design of 2-D recursive digital filters with arbitrary magnitude characteristics, by using all-pass building blocks, is presented. It is shown that in general, cascade of sum or difference of two 2-D all-pass filters with appropriate delay elements are required to guarantee the arbitrary shape of the cutoff boundary of the desired filter. A design example is given to illustrate the usefulness of the proposed technique.

A digitized image that consists of text strings and uniformly distributed background symbols must be segmented if the characters in the text string are to be recognized. This paper describes the development and implementation of morphological approach to character string extraction from regular periodic overlapping text/background images that minimizes the shape distortion of characters. The effectiveness of this algorithm is demonstrated on several test images.>

Multiple expert system is shown to be a promising strategy for handwritten numeral recognition. This paper presents a multiple expert system using neural networks. In the proposed system, the authors have developed (1) an incremental clustering neural network algorithm with merging and canceling process, (2) a modified directional histogram feature extraction method and (3) a subclass method with learning rejection neuron strategy. Our experimental results on a large set of data show the efficiency and robustness of the proposed system.>

Necessary and sufficient conditions are derived (both in m-D analog and discrete domains) which will enable one to realize an m-D transfer function as a sum or a difference of two m-D all-pass transfer functions. This is utilized in the design of 2-D filters whose magnitude response is contained in second and fourth quadrants only.>

A new discrimination function for segmenting touching characters based on both pixel projection and profile projection is presented. A dynamic recursive segmentation algorithm is developed for effectively segmenting touching characters. Contextual information and a spelling checker are used to correct errors caused by incorrect recognition and segmentation. The 99.85% top recognition accuracy has been achieved, while the minimum accuracy is 99.4% based on 12 real documents.>

Queueing formulations are presented for trading nodal storage capacity (SC) with the incremental transmission capacity (TC) of links in supra-high-speed (i.e., >10/sup 8//bps) packet-switched communication networks. The performance criterion used is the mean nodal forwarding time. The results are useful for designing all-optical packet-switching telecommunication networks where the designer needs to compute the amount of incremental TC (ITC) needed to eliminate a specified number of nodal buffers (SC) while preserving the mean nodal forwarding time.>

Presents the results obtained in a performance evaluation study on the recognition of handwritten numerals, using a statistical classifier and a neural network. The features consist of direction sensitive spatial features derived from the digitized image of the numeral. Studies with a large numeral database indicate that the overall performance of the neural net is better than that of the statistical classifier.>

The application of moment invariants to shape and pattern recognition problems is discussed. Zernike moment invariants and pseudo-Zernike moment invariants are derived in a new generalized form for the nth order. A new normalization procedure which improves the discrimination power of both Zernike and pseudo-Zernike moment invariants for handwritten numerals is also presented.>

A novel algorithm for the determination of surface shapes from intensity measurements is presented. The proposed model allows the estimation of the normals at any point on the surface and of the depth at any point in the image plane along the viewer (camera) direction. Simple shape descriptors for characterizing most developable surfaces are derived. It is shown that the principal curvatures of the surface are simply eigenvalues of the restriction of the shape matrix to the tangent space. The proposed algorithm allows incorporation of prior information obtained from stereopsis and other vision processes. Tests with intensity images have shown the algorithm to be convergent, robust, and accurate.>

An interpolation of the sparse depth map of stereopsis is a necessary accomplishment in early vision. A neural implementation of a class of interpolants, known as the Shepard surfaces, is discussed. The computing nature of neurons is exploited, and the results suggest that a variety of early visual functions could be neurally realized in this fashion.>

Algorithms are presented that are capable of restoring images degraded by a variety of corrupting noise sources. These include any combination of additive and/or multiplicative Gaussian noise, focus blur and nonlinear distortion. A parallel implementation of the algorithm is shown to be feasible.>

Restoration of noisy images through the use of a Gibbs field model for the image and a Gaussian random field characterization of the corrupting noise is discussed in this paper. Two new algorithms capable of parallel implementation are presented and shown to yield satisfactory restoration of images corrupted by high levels of noise.

A method is presented for the design of a class of two-dimensional (2-D) stable digital filters satisfying prescribed magnitude of constant group delay specifications. The design method generates a 2-D digital transfer function which is a product of two transfer functions, H1(z1,z2) and H2(z1,z2), corresponding to a recursive filter and a nonrecursive filter, respectively. Component H1(z1,z2) ensures a wave-digital realization, that is, the design method guarantees the generation of a corresponding analog function H1A(s1,s2) which is realizable as the transfer function of a doubly-terminated two-variable lossless network. Thus the design technique ensures that not only a given frequency response is achieved but also the generated transfer function is realizable as a cascade of a wave-digital filter and a nonrecursive digital filter. The class of filters considered here is one in which the doubly-terminated analog network used to realize the wave digital filter is a cascade s1-and s2-variable lossless two-ports with all of their transmission zeros at infinity.

In this paper, necessary and sufficient conditions are given, under which a two-variable rational function can be realized as the transfer, function of a doubly-terminated cascade of s1and s2-variable lossless two-ports, each two-port with all of its transmission zeros at the origin or infinity. Using the above conditions, transfer function of a 2-variable analog reference filter is generated. Parameters of this transfer function are used as parameters of optimization to minimize the least mean square error between the amplitude response of the desired and designed filters. It is shown that the method can also be modified to incorporate the phase and magnitude response of the 2-D filters. To illustrate the method, examples are given.

This paper presents a technique for the design of 2-Dimensional (2-D) stable recursive digital filters satisfying prescribed magnitude and constant group delay response. This technique uses the properties of positive definite matrices and their application in generating 2-variable Very Strictly Hurwitz Polynomials (VSHP) which will be assigned to the denominator of a 2-D analog reference filter. Bi-linear transformations is then applied to the transfer function of the 2-D analog reference filter to obtain the discrete version of the 2-D filter. Parameters of the discrete 2-D filter can be used as the variables of optimization to minimize the least mean square error of the desired and designed magnitude and group delay response of the filter. This technique is illustrated by examples.

This paper presents a method for the design of (N-D) analog and digital recursive filters. The method is based on the properties of multivariable positive real functions, and results in an approach wherein the stability of the filter is guaranteed. The method is illustrated by examples.