High level of integration has led to the advent of Multiprocessor System-on-Chip (MPSoC) which consists of multiple processor cores and accelerators on the same die. A MPSoC programming model is based on a task graph where tasks are assigned to cores to maximize performance. To address thermal hotspots in MPSoCs, coarse-grain power management techniques based on Dynamic Frequency Scaling (DFS) are widely used. DFS is reactive in nature and has detrimental effects on performance. We propose an alternative solution based on dynamic task rescheduling where a temperature prediction scheme is built into the scheduler. The temperature look-ahead scheme is used for task reassignment or delay insertion in scheduling. Since temperature prediction and task assignment are done at runtime, both must be simple and extremely fast. To that end, we propose a heuristic solution based on a limited branch-and-bound search and compare results against an optimal Integer Linear Programming (ILP)-based solution. The proposed approach is shown to be superior to frequency scaling, and the resulting schedule length is within 5% to 10% of the optimal solution as obtained from ILP formulation.

Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved significantly if temporal and Boolean relationships are taken into consideration. Previously, it was shown that worst case switching current in a subset of gates may imply that some other gates may not have the worst case switching condition due to logical relationship between input patterns of a gate. In this paper, we also take integer gate delays into consideration to show that gate switching events may be spaced out in time leading to lower peak current. Further, it is found that taking gate delays into account actually simplifies the size of individual problem instances to be solved, leading to both a faster and more accurate solution. Finally, we compare peak current waveform generated by the proposed solver against SPICE simulation to demonstrate effectiveness of the proposed solution.

Localized heating leads to generation of thermal hotspots that affect the performance and reliability of an integrated circuit (IC). Functional workloads determine the locations and temperatures of hotspots on a die. In this paper, we present a systematic approach for developing a synthetic workload to maximize the temperature of a target hotspot. Our approach is based on the observation that hotspot temperature is determined not only by the current activity in that region, but also by the past activities in the surrounding regions. Accordingly, we develop a wavelet-based canonical spatio-temporal heat dissipation model for program traces, and use a novel integer linear programming formulation to rearrange program phases to generate target worst case hotspot temperature. Program phase behavior is rooted in the static structure of programs. In this case, the initial set of program phases is extracted from the SPEC 2000 benchmark. We apply this formulation to target another well-known problem of maximizing the temperature between a pair of coordinates in an IC. Experimental results show that by taking the spatio-temporal effect into account, we can raise the temperature of a hotspot higher than what is otherwise possible. Hotspot temperature maximization is important in design verification and testing.

Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk on long signal nets is of particular concern. A typical long net is capacitively coupled with multiple aggressors and also tend to have multiple fan-outs. Gate leakage current that originates in fan-out receivers, terminates in the driver causing a shift in driver output voltage. This effect becomes more prominent as gate oxide is scaled more aggressively. Thus, in nano-scale CMOS circuits, noise margin gets eroded by both aggressor crosstalk noise as well as gate leakage loading from fan-outs. In this paper, we present an automatic test pattern generation solution which uses 0-1 integer linear programming to maximize the cumulative voltage noise at a given victim net because of crosstalk and loading in conjunction with propagating the fault effect to an observation point. The target ISCAS benchmark circuits are assumed to have unit gate delays. Results demonstrate both the viability of a solution as well as a need to consider both sources of noise for signal integrity analysis. Pattern pairs generated by this technique are useful for both manufacturing test application as well as signal integrity verification.

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Crosstalk faults have emerged as a significant mechanism of circuit failure due to decreasing process geometries and increasing operation frequencies. Long signal nets are highly susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. Moreover, a typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk induced delay on a victim net, it may be impossible to activate all aggressors logically or simultaneously to constructively induce maximum noise at the victim. Therefore, pattern generation must focus on activating a maximal subset of aggressors, weighted by actual coupling capacitance value, in close temporal proximity of the victim net transition. This max-satisfiability problem is constrained by fault effect propagation condition which involves determining an input signal assignment so as to propagate the fault effect at the victim to the primary output. In this paper, we present Automatic Test Pattern Generation (ATPG) solutions for multiple aggressor crosstalk faults for zero and unit delay models and compare the magnitude of crosstalk induced delay at the victim net. Our solution involves a combination of 0-1 Integer Linear Programming (ILP), for maximal aggressor excitation. Fault effect propagation is solved independently by using traditional stuck-at fault ATPG or by generating additional ILP constraints thus forming a integrated ILP formulation with error propagation. The effect of gate delays is summed by circuit transformation. The proposed technique was applied to ISCAS85 benchmark circuits. Results indicate that the percentage of total capacitance that can be switched varies from 75-100% for zero delay and 30-80% for variable delay case while achieving propagation of the fault effect to primary output.

A significant increase in power density in modern nano-electronic VLSI circuits has lead to increased localized heating and generation of hot spots. These temperature effects can lead to reliability and performance problems. This paper presents a novel design time temperature aware methodology which consists of using additional routing known as Heat Pipes, to transfer heat from hot to cold regions. In order to evaluate the effect of Heat Pipes, a thermal model to simulate effect of metal interconnect on heat distribution is also developed. Results show a 5% to 7% decrease in temperature variation through-out and 2 to 3 degree reduction in hotspot temperature as a result of Heat Pipes.

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies, and the trend is expected to get worse. The measurement unit for failures due to soft errors is failure in time (FIT) that represents the number of failures encountered per billion hours of device operation. FIT rate measurement is time consuming and calls for accelerated testing. To improve effectiveness of soft-error rate (SER) testing, the patterns must be targeted toward detecting node failures that are most likely. In this paper, we present a technique for identifying soft-error-susceptible sites based on efficient electrical analysis that treats soft errors as Boolean errors but uses analog strengths to decide whether such errors can propagate to the next stage. Next, we present pattern generation techniques for manifestable soft errors such that each pattern targets a maximal set of soft errors. These patterns maximize the likelihood of detecting a soft error when it occurs. The pattern generators target scan architecture. It is well known that scan test time is dominated by scan shifts, when no useful testing is being done. To improve efficiency of scan-based testing, we extend the functionality of the existing built-in logic block observation (BILBO) architecture to support test-per-clock operation. Such targeted pattern generation and test application improve SER characterization time by an order of magnitude.

Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk is one of the causes of such kind of failures. Crosstalk fault results from switching of neighboring lines that are capacitively coupled. Long nets are more susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net has multiple aggressors. In generating patterns to create maximal crosstalk noise, it may not be possible to activate all aggressors at the same time. Therefore, pattern generation must focus on activating a maximal subset of aggressors weighted by actual coupling capacitance values. This is a variant of max-satisfiability problem. Unlike a traditional max-satisfiability problem, here we must deal with signal propagation to an observable output. In this paper, the authors present a novel solution that combines 0-1 integer linear program (ILP) with traditional stuck-at fault ATPG. The maximal aggressor activation is formulated as a linear programming problem while the fault effect propagation is treated as an ATPG problem. The problems are separated by min-cut circuit partitioning technique based on Kernighan-Lin-Fiduccia-Mattheyses (KLFM) method. This proposed technique was applied to ISCAS 85 benchmark circuits. Results indicated that 75-100% of the aggressors could be switched for generating crosstalk noise while satisfying requirement of sensitizing a path to the output

In this paper we propose a technique for increasing the rate of failure due to soft errors by carefully choosing the patterns for soft-error detection. It is well known that all circuit nodes are not equally vulnerable to soft error. We propose a metric for measuring vulnerability of a node to soft-error. The pattern selection approach constructs a test set to maximize the node vulnerability metric. In order to facilitate scan based application of these tests, we propose a test-per-clock DFT scheme that allows counting of such errors. The test set thus derived is applied repeatedly to accelerate the soft error rate measurement. Acceleration reported for this technique over random pattern testing on ISCAS-85 benchmarks ranges from 5X to infinity.

Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now become comparable to the switching current. Traditionally, dynamic power and leakage power are computed separately. Dynamic power computation does not include leakage from non-switching nodes. In this paper, we show that in upcoming 45nm technology, leakage from non-switching nodes can account for as much as 38% of total dynamic current. Hence leakage from non-switching nodes can not be neglected during dynamic power computation. To facilitate this study on large benchmark circuits on which spice level simulation is impractical, we created a compact simulation model for modeling various pattern dependent leakage currents to allow leakage computation at gate level. Using a simulation based experiment we compare leakage and switching currents on ISCAS-85 benchmark circuits. The experiments are based on Berkeley predictive technology model for 45nm technology. The results firmly establish the need to consider leakage from non-switching nodes during dynamic power computation.

Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk noise on a net, it may not be possible to activate all aggressors logically or simultaneously. Therefore, pattern generation must focus on activating a maximal subset of aggressors switching around the same time the victim net switches. This is a well-known problem. In this paper, we present a novel solution assuming a unit delay model for the gates, combining 0-1 integer linear program (ILP) with traditional stuck-at fault ATPG. The maximal aggressor activation is formulated as a linear programming problem while the fault effect propagation is treated as an ATPG problem and the gate delays are subsumed by a circuit transformation. The proposed technique was applied to ISCAS 85 benchmark circuits. Results indicate that percentage of total capacitance that can be switched varies from 30-80%.

Max-current analysis is essential in power rail design and power supply switching noise analysis. Traditionally, maximum current from all CMOS gates are added together to compute maximum current level. This approach ignores all Boolean relationships. The problem of finding the input vector pair that will cause worst case current draw from the power rails when Boolean relationships are considered is an NP-hard problem. In this paper, we propose a Current Maximizing Pattern Generation (CMPG) algorithm which greatly reduces the computational complexity by using a parameterized branch-and-bound heuristic that prunes the search space by looking for a lower as well as an upper bound for maximum switching currents. When allowed to proceed indefinitely, the CMPG algorithm converges on an exact solution instead of finding upper and lower bounds. When coupled with a switch level SAT solver, CMPG can generate patterns for cell library characterization.