A BJT based resistor-less bandgap reference circuit in 65nm CMOS is presented. High impedance switched-capacitor-based resistors replace the standard diffusion resistors in a current mode architecture. Switch conductance and leakage are controlled by an internally generated boosted voltage and a negative clock signal circuit. To start up the BGREF, a low current injection method is applied in sensitive nodes of the design. The circuit occupies 0.0106 mm${}^{\mathbf {2}}$and has a power consumption of 8 nW from a 0.85 V supply. Independent trimming of the temperature coefficient and output voltage is presented, both of which are required for high volume manufacturing. After a two-point calibration process, a measurement of 31 units exhibited a mean temperature drift of 111 ppm/°C, a PSRR of -38 dB and an accuracy of 0.59% at$30~^{\circ }$C.

This article presents a novel sensing scheme for a 2T gain-cell embedded dynamic random access memory (GC-eDRAM) optimized for cryogenic temperatures. The proposed design integrates a highly accurate sense amplifier (SA) with a$\pm 3\sigma $sensitivity of 11.16 mV and an internally generated, adjustable reference voltage (VREF) with 9.5 mV step resolution. Additionally, an on-chip ring-oscillator-based design-for-test (RO-DFT) mechanism is introduced to determine the optimal VREF postfabrication, improving readout reliability while adapting to process variations. Simulation results, based on a 65nm CMOS process calibrated for 77 K operation, demonstrate a significant extension of the data retention time (DRT) to 80 ms, reducing refresh cycle frequency and lowering power consumption—critical for cryogenic applications such as infrared imaging. The proposed architecture provides a power-efficient, high-density embedded memory solution for low-temperature computing environments.

A Dynamic Continuous-Time Zoom-ADC current to digital converter for bio-sensing applications is presented, comprising a current DAC (IDAC), a loop filter, a comparator, and loop logic. Within the IDAC, a reference voltage is driven to resistor legs, obtaining an accurate current with high Rout. A$1^{\mathrm {st}}$order loop filter utilizes an inherently linear, zero-static-power, passive integrator. An isolation of the integrator from external sensor capacitance is obtained by a cascode transistor, enabling the use of the passive integrator. During the Zoom’s SAR phase, a binary search detects the approximate signal level and provides zoomed references for the Sigma-Delta phase, where fine conversion is performed. The dynamic mode tracks the comparator output data to determine when the input signal is close to the references and updates them accordingly. This paper is the first to propose a dynamic zoom ADC which utilizes a single DAC. An over-voltage detector detects integrator voltages exceeding the supply level, a result of high input currents, and prevents damage to the circuit. A 65nm implementation achieved a competitive dynamic range of 125dB, an SNR of 91dB and an FoM of 192dB. The design occupies 0.08 mm2, and a state-of-the-art power consumption of 11.4uW was measured. The dynamic mode supports up to 78Hz inputs, and an SFDR of 90.4dB was measured.

PUF circuits utilize multiple identical bit-cells to generate their unique keys. Thus, the Si area of each bit has a profound impact on the circuit. A method for extraction of multiple independent bits from single PUF cells is proposed. This method utilizes PUF preselection ‘tilt’ tests to obtain a new, uncorrelated, entropy source. During tilt tests, intentional controllable mismatch is introduced to the PUF cells, and their stability is concluded. The test could be revisited as a method to measure the internal mismatch size, by finding the tilt size required to flip the test result from ‘pass’ to ‘fail’. As the mismatch size is random and uncorrelated, it could be used to extract multiple additional PUF bits, as well as to find the unstable bit-cells relative to each new PUF bit. A Si implementation, which relies on the capacitive tilt PUF, in TSMC 65nm, is presented, with two additional bits. This demonstrates the applicability of the scheme for multiple new bits. Measured results of the second new bit show BER of 4E-4, zero additional cell area and excellent uniqueness and randomness.

Temperature monitoring and regulation is a critical power/performance feature in microprocessors. Due to the multiplicity of hotspots, a large number of on-die sensors are utilized. This requires them to be highly compact, low energy and fast. A miniaturized current controlled oscillator (CCO) sensor is described for this application. It has an area of only 700$\mu \text{m}^{2}$in the 16-nm FinFET process, with an energy consumption of 0.25 nJ in a 6.9-$\mu \text{s}$conversion. The inaccuracy is within ±1.5 °C peak-to-peak (p-p) over a 130 °C range, at a resolution of 0.32 °C. These characteristics make the circuit attractive for high-density thermal sensing.

This paper presents a self-biased subthreshold voltage reference with several types of trimming options. A current trim is used to achieve similar currents across process corners. A coarse/fine voltage trim was implemented, which utilized different Vth's of the process as well as the reverse short-channel effect. The range of voltages obtained vary from 86mV to 536mV with steps of 16mV. The circuit was designed in a standard 0.18 μm CMOS process. Simulation results at Vcc=3D1V shows a temperature coefficient (TC) between 40 to 400 ppm/oC at different trims over a 120oC range. The nominal power consumption was 1.35nW with a highly compact area of 0.002 mm2.

An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2per bit.

An Offset Canceled Bandgap Reference (BGREF) circuit is reported in TSMCs 28nm technology node. This BGREF has a 3-sigma untrimmed inaccuracy of ±0.534% with a power consumption of 58uW and an estimated area of 2142um2 which is one of the smallest BGREFs reported. The BGREF uses a closed loop circuit with a Folded Cascode Amplifier.

A miniaturized thermal sensor for use in Intel's microprocessors has been demonstrated in a cutting-edge purely digital process. The circuit shows nearly linear frequency dependence with temperature of 45kHz/°C. The circuit occupies 3.75 × 10-3mm2and consumes a current of ~700uA, which makes it suitable to be placed in array on a microprocessor to measure thermal gradients across the die.

A novel on-chip linear voltage regulator (VR), for use as PLL power supply is described. This voltage regulator exhibits a Power Supply Rejection Ratio (PSRR) of > 40dB and low thermal noise. Accurate current control enables optimized power and performance. These properties enable the VR to be utilized in PLL's without adding any deterministic and random jitter. The VR has been designed and characterized in Intel's recent leading-edge purely digital process.

Several new building blocks are demonstrated, which enable low-power (1.1-1.8V) analog functionality in a single-poly, digital CMOS process. These cells facilitate the integration of analog converters on system-on-a-chip IC’s without adding any extra cost to the process. A voice A/D, designed with these circuits, exhibited an SNR of 68 dB at an analog supply voltage of 1.1V, and 75dB at 1.8V. This is despite the noisy digital environment of an on-chip DSP operating at 60 Mhz and a digital supply voltage of 2.5V. 2.