This brief presents a current-steering 25-GS/s 8-bit digital-to-analog converter (DAC) based on a 40-nm CMOS technology. The DAC employs a dual-edge sampling (DES) architecture to reduce the requirement of main clock frequency, optimizing switching noise and improving power efficiency. DES is sensitive to the clock duty cycle. To minimize the image tones and performance degradation caused by duty-cycle errors, a single-slope analog-to-digital converter (ADC)-based duty-cycle detection and correction scheme is proposed, achieving closed-loop background calibration. A T-coil output network is used to extend the bandwidth. The proposed DAC achieves a spurious-free dynamic range (SFDR) of >40 dBc up to the Nyquist frequency and a >12-GHz output bandwidth with sinc roll-off compensation. The active power consumption is about 272 mW under 1.8-/0.9-/−1.8-V power supply.

This brief reports on a 13-GHz quad-core voltage-controlled oscillator (VCO) using a folded S-shaped tail inductor. The contribution of this work is that the auxiliary resonator is folded into the main inductor, so that it leads to a more compact solution than a conventional scheme. Due to the S-shaped inductor’s electromagnetic (EM) characteristics, the proposed tail filter can achieve noise suppression without EM interference to the main tank. Designed and implemented in a 28-nm CMOS process, the proposed VCO operates between 12.32 and 13.84 GHz, for an 11.6% turning range. The measurements were carried out in the free-running mode, and the results show a phase noise (PN) of 118.3 dBc/Hz at a 1-MHz offset from the central frequency of 12.32 GHz. The power consumption of the VCO core is 24.5 mW, with a 0.9-V supply voltage, and this leads to a figure of merit (FoM) of 186.6 dBc/Hz.

This brief presents a novel compact double-pole triple-throw switch based multi-phase integrated 6-bit passive phase shifter. An innovative topology adopts one high-pass circuit and two low-pass circuits connected in parallel via double-pole triple-throw switch is proposed to replace 22.5° and 45° inductor-based bridged T-type phase shifting cells for 50% chip size reduction. Furthermore, in 5.625° phase shifting cell, a novel topology whose phase error is smaller than 0.05° is proposed by adopting a phase shifting fluctuation optimization unit and two low-pass circuits connected in parallel. The proposed phase shifter is implemented in 55 nm CMOS technology. Electromagnetism simulation results show that the root-mean-square (RMS) phase error of this phase shifter is 2.5°~4.2° from 14 to 18 GHz. An average insertion loss (IL) of -13.1±2.1 dB is achieved. The core chip area is 1.2*0.62 mm2.

This brief presents an explicit Class-F23 voltage-controlled oscillator (VCO). The square-like voltage waveform is obtained via waveform shaping, and flicker noise upconversion is suppressed by a proper common-mode (CM) return path. CM resonance at the second harmonic frequency is introduced by a compact octagonal inductor. The rms value of the impulse sensitivity function (ISF) is significantly reduced through Class-F23 operation. The VCO switches between two modes of a high-order LC resonator consisting of two identical LC tanks coupled by capacitors. A prototype of the VCO is implemented in a 28-nm CMOS. Measurements show a continuous tuning range (TR) of 4.89–7.29 GHz, with a peak figure of merit (FoM) of 190.5 dB/Hz at 5.8 GHz and better than 188.5 dB across the entire TR. The flicker phase-noise corner ranges from 70 to 400 kHz. The VCO consumes 16–19 mW from a 0.5-V supply and occupies an active area of 0.21 mm2.

This article proposed a deep-pipelined analog-to-digital converter (ADC) that utilizes an input-split fully differential ring amplifier (ringamp, RAMP). The implemented ringamp is optimized for speed, achieving a higher nondominant pole frequency, and exhibits excellent adaptability in low-voltage, deep-nanoscale advanced CMOS processes. To minimize nonoverlap time, a nonoverlapping optimized clock generator is employed, generating two-phase and nonoverlapping clocks with near 50% duty cycles for sampling and amplification in the multiplying digital-to-analog converters (MDACs). The ADC architecture comprises a high-linearity input buffer, ten MDACs, and a flash backend ADC. To enhance linearity, a dither signal is injected in the first three stages. Fabricated in a 28-nm CMOS process, the 1-GS/s 12-bit ADC based on the ringamp achieves a spurious-free dynamic range (SFDR) of 70.34 dB and a signal-to-noise-and-distortion ratio (SNDR) of 55.71 dB at Nyquist input, while consuming only 38.9 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 75 fJ/conversion step and a Schreier FoM of 157.2 dB, respectively.

In this paper, a time-interleaved 10GS/s 8bit ADC fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. The proposed 4×4 input multiplexer allows the ADC to support 1/2/4-channel sampling modes with no compromised isolation and input bandwidth. In the THA stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the output overshot effect of the SEF. The measurement result shows that the ADC has a SFDR >43dBc over the entire Nyquist frequency. It has an effective number of bits (ENOB) about 6.6 at low frequency and dropping to 5.5 at 5GHz.