Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.

With increasing chip complexities and the requirement to reduce design time, early analysis is becoming increasingly important in the design of performance critical CMOS chips. As clock rates increase rapidly, interconnect delay consumes an appreciable portion of the chip cycle time, and the floorplan of the chip significantly affects its performance. This paper describes a system for early floorplan analysis of large designs. The floorplanner is designed to be used in the early stages of system design, to optimize performance, area and wireability targets before detailed implementation decisions are made. Most floorplanners which claim to optimize timing work only on a subset of paths during the floorplanning process. One novel feature of our floorplanner is that it performs static timing analysis during the floorplan optimization process, instead of working on a subset of the paths. The floorplanner incorporates various interactive and automatic floorplanning capabilities. The paper describes the floorplanning capabilities and algorithms as well as our experiences in using the tool.

An approach to early floorplanning in which optimization of a CPU chip floorplan is done in the context of a program benchmark (workload) is presented. The methodology integrates workload-driven cycles-per-instruction estimation into the traditional cycle-time evaluation process implied by an (early) floorplanning tool. This effectively adds an extra dimension to the floorplanning optimization cost function and search space, allowing superior MIPS-tuning of the VLSI chip.>

The problems associated with optimization of the test application timing for a class of test equipment are identified. Two approaches to test application timing are introduced. The notion of slack is used to define the objective function for optimization. The optimization problem is shown to be NP-complete even for nonreconvergent-fanout circuits. Heuristics for the optimization problems are presented, and the results are compared with bounds on test circuits.>

The increasing emphasis on AC testing of integrated circuits is driven by the combination of tighter quality requirements and sensitivity of high performance circuits to delay defects. The areas of fault modeling, fault simulation and test generation as applied to AC testing have received most of the attention so far. The relatively unexplored side of AC test is the determination of the test application timing. Tight timings during test application are crucial to the success of the AC test. This paper formulates the problem of generating tight test application timings and presents some sample results using a heuristic algorithm.

A generalization of the min-cut partitioning problem, called min-cost tree partitioning, is introduced. In the generalized problem. the nodes of a hypergraph G are to be mapped onto the vertices of a tree structure T, and the cost function to be minimized is the cost of routing the hyperedges of G on the edges of T. The standard min-cut problem is the simple case in which the tree T is a single edge connecting two vertices. Several VLSI design applications for this problem are discussed. An iterative improvement heuristic for this problem in which nodes of the hypergraph are moved between the vertices of the tree is described. The running time of a single pass of the heuristic for the unweighted version of the problem is Q(P*D*t/sup 3/), where P is the total number of pins in the hypergraph G, D is the maximum number of nodes in a hyperedge of G, and t is the number of vertices in the tree T. Several test results are discussed.>

An approach to the constraint-based floor planning of flexible, fixed, and preplaced blocks that is based on the removal of redundant constraints and the reshaping of flexible blocks is discussed. A floor plan is said to respect a given constraint set if is satisfies either a vertical or a horizontal constraint in the set for each pair of blocks. The approach presented is to construct a floor plan of optimal area that respects the input constraint set, which is assumed to be derived from a relative placement of the blocks. Reasons for considering this method are delineated, and a heuristic floor-planning algorithm based on constraint reduction and block reshaping is given. A simple example illustrates the algorithm. Several real floor-planning examples are also given.>

The problem considered is that of producing a legal floorplan that respects a given topological constraint set. The floorplanning approach described is targeted for multilayer sea-of-cells based designs. Therefore it is assumed that no channel separations are required between the blocks. The approach can be generalized to incorporate channel separations.>

The problem of minimizing the number of power pads, in order to guarantee the existence of a planar routing of multiple power nets, is discussed. A general lower bound is derived, and a heuristic for the general problem is discussed. Several important special cases, including the case of three power nets, are examined, and optimal strategies for pad placement are presented. It is also shown that the general pad minimization problem is NP-complete.>

The layer assignment problem that arises in the design of a multichip module, a high-performance compact package for the interconnection of several hundred chips, is studied. The aim is to place each net in a x-y pair of layers, so as to minimize the number of such pairs. An approximation algorithm, running in O(nd) time is presented for minimizing the number of layers, where n is the number of nets and d is the (two-dimensional) density of the problem.>

An approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST), is discussed. The main idea in this approach is to find layouts for the edges of the MST that maximize the overlaps between the layouts, thus minimizing the cost (i.e. wire length) of the resulting rectilinear Steiner tree. Two algorithms for constructing rectilinear Steiner trees from MSTs, which are optimal under the conditions that the layout of each edge of the MST is an L shape or any staircase, respectively, are described. The first algorithm has linear time complexity and the second algorithm has a higher polynomial time complexity. Steiner trees produced by the second algorithm have a property called stability, which allows the rerouting of any segment of the tree, while maintaining the cost of the tree, and without causing overlaps with the rest of the tree. Stability is a desirable property in VLSI global routing applications.>

The problem of partitioning logic onto the vertices of a partition graph G such that the cost of routing the global nets of the partition on the edges of G is minimized is discussed. This is referred to as the min-cost partitioning on a graph (MCPG) problem. The MCPG problem generalizes previously studied partitioning problems, such as classical min-cut, the quadrisection approach, min-cost tree partitioning, and multiple way network partitioning. Some applications of this partitioning model are discussed, a framework for its solution is described, and experimental results are presented.>

We discuss a new approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST). The main idea in our approach is to determine L-shaped layouts for the edges of the MST, so as to maximize the overlaps between the layouts, thus minimizing the cost (i.e., wire length) of the resulting RST. We describe a linear time algorithm for constructing a RST from a MST, such that the RST is optimal under the restriction that the layout of each edge of the MST is an L-shape. The RST's produced by this algorithm have 8-33% lower cost than the MST, with the average cost improvement, over a large number of random point sets, being about 9%. The running time of the algorithm on an IBM 3090 processor is under 0.01 seconds for point sets with cardinality 10. We also discuss a property of RST's called stability under rerouting, and show how to stabilize the RST's derived from our approach. Stability is a desirable property in VLSI global routing applications.

We introduce a generalization of the min-cut partitioning problem, called Min-Cost Tree Partitioning, in which the nodes of an hypergraph G are to be mapped on to the vertices of a tree structure T, and the cost function to be minimized is the cost of routing the hyperedges (i.e., the nets) of G on the edges of T. We discuss several interesting VLSI design applications for this problem. We describe an iterative improvement heuristic for solving this problem.

A polynomial time algorithm is given for constructing the minimum cost rectilinear Steiner tree (RST) that is derivable from a minimum spanning tree (MST) of a given point set, such that the MST edges have staircase layouts in the RST. RSTs produced by the algorithm have a property called stability, which enables the rerouting of any subset of the RST edges, while maintaining the cost of the RST, and not causing overlaps with each other or with the other RST edges.>

A description is given of the VHV-channel-routing problem in irregular channels. The authors describe a branch-and-bound algorithm for finding optimal solutions for this problem. The algorithm partitions the channels into boxes and searches for the optimal among the various mappings of the horizontal net segments to the boxes. The authors discuss three different branching strategies for the algorithm. Heuristic algorithms based on the branching strategies are also discussed. It is also shown that VHV routing is NP-hard for irregular channels.>

Article Free Access Share on Geometry of planar graphs with angles Author: V Vijayan School of Information and Computer Science, Georgia Institute of Technology, Atlanta, Georgia School of Information and Computer Science, Georgia Institute of Technology, Atlanta, GeorgiaView Profile Authors Info & Claims SCG '86: Proceedings of the second annual symposium on Computational geometryAugust 1986Pages 116–124https://doi.org/10.1145/10515.10528Published:01 August 1986Publication History 14citation537DownloadsMetricsTotal Citations14Total Downloads537Last 12 Months95Last 6 weeks13 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The embedding problem for a class of graphs called rectilinear graphs is discussed. These graphs have applications in many VLSI Layout Problems. An interesting topological characterization of these graphs lead to efficient algorithms for recognizing and embedding rectilinear graphs which are embeddable on the plane.

The first component of a VLSI (very large-scale integration) design environment being built at Princeton University is described.The general theme of this effort is to make the design of VLSI circuits as similar to programming as possible.The attempt is to build tools that do for the VLSI circuit designer what the best software tools do for the implementer of large software systems.

ALI is a procedural language to specify VLSI layouts. It allows the designer to describe layouts without reference to the sizes and positions of the layout elements or to the distances between them. Among the interesting characteristics of ALI are that it does not need design rule checking, is easy to extend, facilitates the division of labor and permits the easy update of a layout to new design rules or to new processes. The general features of the language and the experience gained with a preliminary implementation of it are described.